Dates and Events: |
OSADL Articles:
2023-11-12 12:00
Open Source License Obligations Checklists even better nowImport the checklists to other tools, create context diffs and merged lists
2022-07-11 12:00
Call for participation in phase #4 of Open Source OPC UA open62541 support projectLetter of Intent fulfills wish list from recent survey
2022-01-13 12:00
Phase #3 of OSADL project on OPC UA PubSub over TSN successfully completedAnother important milestone on the way to interoperable Open Source real-time Ethernet has been reached
2021-02-09 12:00
Open Source OPC UA PubSub over TSN project phase #3 launchedLetter of Intent with call for participation is now available |
Real Time Linux Workshops
1999 - 2000 - 2001 - 2002 - 2003 - 2004 - 2005 - 2006 - 2007 - 2008 - 2009 - 2010 - 2011 - 2012 - 2013 - 2014 - 2015
14th Real Time Linux Workshop, October 18 to 20, 2012 at the Department of Computer Science, University of North Carolina at Chapel Hill
Announcement - Call for papers (ASCII) - Hotels - Directions - Agenda - Paper Abstracts - Presentations - Registration - Abstract Submission - Sponsors - Gallery
On-chip cache coherence and real-time systems
Paul McKenney, IBM Linux Technology Center
In the Communications of the ACM article entitled "Why On-Chip Cache Coherence Is Here to Stay", Martin et al. argue that on-chip cache coherence can scale for the foreseeable future, with only modest impact on performance, even for very large systems. Unfortunately, a number of the authors' arguments apply only to non-real-time systems. For example, the authors in some cases discuss amortization of overheads across operations, which addresses non-real-time scalability concerns, but fails to address the worst-case overheads that real-time workloads are sensitive to.
One possible position is that real-time response is important only on relatively small systems. Although this position might seem reasonable in light of the fact that until quite recently, real-time systems were almost always uniprocessors, recent Linux-kernel bug reports complaining of 200-microsecond latency spikes on systems with 4096 CPUs present a counterexample, albeit a surprising one. In light of this counterexample, it is reasonable to take another look at the arguments presented in "Why On-Chip Cache Coherence Is Here to Stay" with an eye to how they apply to real-time systems. This talk will take up this task, delineating what is required for highly scalable real-time systems.