Sergio A. Rodríguez and Phillip M. S. Burt, Escola Politécnica, University of São Paulo, Brazil

This paper develops a new qualitative latency model of the Linux 2.6 OS for the Intel x86 architecture. The proposed model analyses aspects related to digital signal processing in real time. In this context, the study identifies all latency sources since the arrival of a signal sample (or block of samples) up to the execution of the first instruction related to processing that sample. The interrupt latency is divided into seven components, including hardware latency sources such as microprocessor operation and interrupt controller queue. The dispatch latency is divided into six components, adding new components such as interrupts stack latency and deferrable functions latency to the known sources such as scheduler latency and switch context latency. The paper also identifies further overhead sources such as memory allocation by demand paging. Finally, some of the new latency components are measured using an instrumented kernel. The measures are obtained with and without computational load for the purpose of analyzing its influence in the latency components.