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2025-04-10 - 20:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Thu Apr 10, 2025 12:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134791214168,34phc2sys0-21swapper/307:05:013
29502204171,22sleep10-21swapper/107:07:211
28622200166,22sleep00-21swapper/007:06:110
28392200167,22sleep20-21swapper/207:05:522
345199614,17cyclictest17934-21df_abs12:35:161
345199602,11cyclictest30676-21sed10:30:001
134762590,2sleep20-21swapper/207:30:162
345199584,12cyclictest13466-21head09:40:291
345199572,11cyclictest21658-21sed10:00:271
3450995719,4cyclictest9-21ksoftirqd/011:40:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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