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2025-03-14 - 07:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot4.osadl.org (updated Fri Mar 14, 2025 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
266471699498495,2cyclictest2689225-21turbostat20:14:551
266471699494491,2cyclictest2823538-21turbostat23:39:551
266471699484482,1cyclictest2778540-21turbostat22:39:561
266471699456453,2cyclictest2797395-21turbostat23:00:001
266471699440438,1cyclictest2699448-21turbostat20:35:001
266471699432429,1cyclictest2827873-21turbostat23:44:551
266471699391387,3cyclictest2804601-21turbostat23:10:001
266471699390387,2cyclictest2786608-21turbostat22:45:001
266471699362358,3cyclictest2849748-21turbostat00:10:001
266471699309306,2cyclictest2695098-21turbostat20:25:001
266471699308306,1cyclictest2763682-21turbostat22:19:551
266471699278275,2cyclictest2853703-21turbostat00:15:001
266471699276273,2cyclictest2819410-21turbostat23:30:001
266471699272268,3cyclictest2697059-21turbostat20:30:011
26642612266207,45sleep00-21swapper/019:06:100
266471699255248,5cyclictest2868783-21turbostat00:39:551
266471699254252,1cyclictest2774430-21turbostat22:30:001
26639692253188,30sleep10-21swapper/119:05:301
266471699251245,4cyclictest2864702-21turbostat00:34:551
266471699249242,5cyclictest2681355-21turbostat19:54:551
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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