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2025-04-02 - 08:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot6.osadl.org (updated Wed Apr 02, 2025 00:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
362568699146139,5cyclictest3676891-21kworker/u8:0+events_unbound22:25:020
362568699116106,7cyclictest3608112-21kworker/u8:0+events_unbound19:10:020
362569199114101,10cyclictest3666582-21latency_hist21:30:001
36256919911198,5cyclictest3697089-21kworker/u8:0+events_unbound23:40:241
362569199110104,4cyclictest3632115-21kworker/u8:2+flush-179:019:35:241
36256919910996,11cyclictest3705783-40logrotate00:00:011
36256869910698,7cyclictest3656562-21kworker/u8:3+events_unbound21:20:260
36256869910698,7cyclictest3656562-21kworker/u8:3+events_unbound21:20:250
36256869910694,4cyclictest3638476-21kworker/u8:0+flush-179:019:50:240
36256869910599,4cyclictest3635290-21kworker/u8:1+events_unbound19:45:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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