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2024-07-16 - 06:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackeslot5.osadl.org (updated Mon Jul 15, 2024 12:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14808996529,0cyclictest0-21swapper/009:07:180
14808994524,4cyclictest12035-21ssh09:47:180
1481999330,4cyclictest7850-21diskmemload12:05:473
1481999330,33cyclictest7850-21diskmemload09:49:553
1481999330,33cyclictest7850-21diskmemload09:10:533
1481999330,32cyclictest0-21swapper/311:56:193
14819993228,4cyclictest0-21swapper/309:37:333
1481999320,3cyclictest0-21swapper/309:56:203
1481999320,31cyclictest0-21swapper/312:36:153
1481999320,31cyclictest0-21swapper/311:35:573
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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