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2025-03-31 - 20:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackeslot2.osadl.org (updated Mon Mar 31, 2025 12:43:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
152421221070,1sleep10-21swapper/108:50:191
17337452360,2sleep20-21swapper/211:10:192
17337452360,2sleep20-21swapper/211:10:192
25010912817,2phc2sys0-21swapper/311:59:523
25010912614,2phc2sys0-21swapper/312:06:573
16245502260,1sleep10-21swapper/109:57:001
25010912518,3phc2sys0-21swapper/311:53:063
25010912518,3phc2sys0-21swapper/311:53:053
25010912518,2phc2sys0-21swapper/309:40:073
25010912517,3phc2sys0-21swapper/309:16:273
25010912418,3phc2sys0-21swapper/309:30:373
25010912418,2phc2sys0-21swapper/312:21:563
25010912418,2phc2sys0-21swapper/312:11:213
25010912418,2phc2sys0-21swapper/310:40:343
25010912418,2phc2sys0-21swapper/310:00:463
25010912418,2phc2sys0-21swapper/309:29:293
25010912418,2phc2sys0-21swapper/307:55:323
25010912418,2phc2sys0-21swapper/307:34:203
25010912418,2phc2sys0-21swapper/307:12:163
25010912417,3phc2sys0-21swapper/310:18:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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