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2024-11-25 - 14:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackeslot2.osadl.org (updated Mon Nov 25, 2024 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
264567721140,1sleep00-21swapper/000:30:230
235158621130,1sleep00-21swapper/021:35:250
262395821050,2sleep30-21swapper/300:20:003
2500991340,2ptp4l0-21swapper/321:00:103
2500991280,5ptp4l186990irq/129-enp1s0-TxRx-000:00:103
2500991270,5ptp4l186990irq/129-enp1s0-TxRx-021:20:133
2500991270,5ptp4l186990irq/129-enp1s0-TxRx-019:55:023
2500991260,6ptp4l186990irq/129-enp1s0-TxRx-021:00:013
2500991260,5ptp4l186990irq/129-enp1s0-TxRx-023:52:333
2500991260,5ptp4l186990irq/129-enp1s0-TxRx-023:52:323
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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