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2024-07-16 - 08:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackeslot2.osadl.org (updated Mon Jul 15, 2024 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24781821200,5sleep0171ktimers/010:01:380
35572021170,2sleep00-21swapper/011:07:310
39570021040,2sleep30-21swapper/311:30:193
38166621020,1sleep00-21swapper/011:24:350
1476352970,2sleep30-21swapper/308:56:523
18214992623,1cyclictest0-21swapper/209:25:012
3572412250,1chrt357125-21latency_hist11:10:011
18213992421,2cyclictest382486-21systemd11:25:021
18214992321,1cyclictest0-21swapper/211:05:022
18212992320,2cyclictest506418-21latency_hist12:40:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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