You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-07-16 - 08:23
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Mon Jul 15, 2024 12:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1299911820,6ptp4l401ktimersoftd/307:08:503
1352721750,8sleep31031099cyclictest09:30:193
3053521680,7sleep11030899cyclictest11:15:161
2220021220,6sleep21030999cyclictest12:05:282
9766211090,10sleep10-21swapper/107:06:421
10307998632,6cyclictest9-21ksoftirqd/008:45:390
10307998529,5cyclictest9-21ksoftirqd/010:00:000
10309998311,10cyclictest1-21systemd08:45:042
10307998323,5cyclictest9-21ksoftirqd/011:00:010
10309998111,19cyclictest22862-21sed09:50:152
10309998111,13cyclictest5632-21grep10:20:382
10307997927,5cyclictest9-21ksoftirqd/009:45:360
98222779,56sleep00-21swapper/007:07:270
10309997712,18cyclictest2899-21df_abs11:25:182
10309997711,14cyclictest7344-21cpuspeed_turbos11:35:132
10309997711,14cyclictest31443-21ps11:15:332
10309997711,12cyclictest1-21systemd08:44:412
1030999769,20cyclictest7200-21irqrtprio08:10:292
10309997610,21cyclictest1340-21/usr/sbin/munin09:05:422
1030999759,12cyclictest20670-21ls10:55:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional