You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-11-22 - 09:56
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Fri Nov 22, 2024 00:46:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
439921770,7sleep22228199cyclictest23:05:212
124091169147,9phc2sys0-21swapper/319:08:013
2703721620,7sleep12228099cyclictest20:25:281
57298920,15rtkit-daemon0-21swapper/019:08:100
2228299790,28cyclictest31746-21chrt20:35:543
2228099798,12cyclictest31072-21ls22:55:001
22281997663,8cyclictest33-21ksoftirqd/223:50:082
2228099768,12cyclictest28528-21sed00:00:211
2228299740,27cyclictest29460-21taskset00:03:553
2228099727,12cyclictest4257-21ps23:05:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional