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2025-04-04 - 12:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot4.osadl.org (updated Fri Apr 04, 2025 00:45:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
123842204170,22sleep20-21swapper/219:09:252
123782203170,22sleep10-21swapper/119:09:191
123752202169,22sleep30-21swapper/319:09:163
123272202168,22sleep00-21swapper/019:08:380
12727996534,4cyclictest33-21ksoftirqd/223:40:002
12728996331,4cyclictest41-21ksoftirqd/320:55:143
12727996329,4cyclictest33-21ksoftirqd/223:30:222
12727996224,4cyclictest33-21ksoftirqd/221:50:002
12727996129,4cyclictest33-21ksoftirqd/222:00:162
12727996122,8cyclictest33-21ksoftirqd/219:40:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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