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2025-04-02 - 08:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Wed Apr 02, 2025 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
289302222157,53sleep00-21swapper/019:09:230
137191206172,23phc2sys0-21swapper/319:05:573
286892205172,22sleep10-21swapper/119:06:161
287422202169,22sleep20-21swapper/219:06:562
324382750,1sleep00-21swapper/020:30:150
29273996630,9cyclictest41-21ksoftirqd/323:50:003
29271996523,10cyclictest25-21ksoftirqd/119:55:291
29271996419,9cyclictest25-21ksoftirqd/123:10:171
29273996232,7cyclictest41-21ksoftirqd/321:40:013
29273996224,7cyclictest41-21ksoftirqd/322:50:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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