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2024-11-22 - 10:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot3.osadl.org (updated Fri Nov 22, 2024 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
147591206174,21phc2sys0-21swapper/319:08:183
152822200167,22sleep00-21swapper/019:09:160
151042199165,22sleep10-21swapper/119:07:001
150402197164,22sleep20-21swapper/219:06:092
15629996421,4cyclictest25-21ksoftirqd/120:15:131
15629996325,8cyclictest25-21ksoftirqd/123:25:011
15629996128,4cyclictest25-21ksoftirqd/122:15:271
1562999599,48cyclictest0-21swapper/121:30:291
15629995828,9cyclictest25-21ksoftirqd/119:50:131
15629995825,4cyclictest25-21ksoftirqd/121:55:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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