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2025-04-02 - 08:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackdslot2.osadl.org (updated Wed Apr 02, 2025 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
153042241196,34sleep30-21swapper/319:07:593
151332206172,23sleep20-21swapper/219:05:452
153022204173,20sleep10-21swapper/119:07:571
152232204171,22sleep00-21swapper/019:06:550
229821500,1sleep10-21swapper/119:50:011
137291810,1ptp4l29493-21apt-get23:35:143
31032660,3sleep00-21swapper/023:50:130
137291610,1ptp4l401ktimersoftd/319:55:393
244242570,1sleep00-21swapper/020:40:250
137291560,1ptp4l401ktimersoftd/300:02:353
15754995223,4cyclictest33-21ksoftirqd/223:20:192
137291510,1ptp4l401ktimersoftd/323:21:483
137291510,1ptp4l401ktimersoftd/323:01:383
137291510,1ptp4l401ktimersoftd/320:20:173
137291510,1ptp4l401ktimersoftd/320:20:173
250742480,2sleep30-21swapper/319:30:013
103652470,2sleep30-21swapper/320:10:123
1575599461,3cyclictest121rcu_preempt23:35:003
1575499442,7cyclictest33-21ksoftirqd/220:35:132
137291440,0ptp4l401ktimersoftd/323:49:183
137291430,0ptp4l401ktimersoftd/319:30:313
15752994228,5cyclictest9-21ksoftirqd/000:26:280
1575299421,39cyclictest27353-21cron19:35:000
137291420,0ptp4l401ktimersoftd/320:08:483
1575599414,3cyclictest121rcu_preempt20:35:143
1575499418,4cyclictest33-21ksoftirqd/200:35:212
137291410,0ptp4l401ktimersoftd/321:19:383
1575499402,3cyclictest121rcu_preempt00:30:132
1575499402,3cyclictest121rcu_preempt00:30:132
1575399401,2cyclictest121rcu_preempt00:26:271
137291400,1ptp4l401ktimersoftd/321:11:403
15754993931,5cyclictest33-21ksoftirqd/219:35:142
15754993925,6cyclictest33-21ksoftirqd/221:20:002
1575499391,3cyclictest33-21ksoftirqd/219:40:252
137291390,0ptp4l401ktimersoftd/320:00:283
1575599389,4cyclictest41-21ksoftirqd/319:10:173
1575599383,3cyclictest121rcu_preempt22:30:223
1575599381,2cyclictest121rcu_preempt19:25:003
1575599381,2cyclictest121rcu_preempt19:25:003
15754993833,3cyclictest14721-21sh21:35:002
15754993833,2cyclictest33-21ksoftirqd/200:10:002
15754993824,3cyclictest33-21ksoftirqd/221:40:002
15754993823,3cyclictest33-21ksoftirqd/223:00:182
15752993832,4cyclictest9-21ksoftirqd/019:28:370
1575599376,3cyclictest41-21ksoftirqd/323:15:223
1575599376,3cyclictest121rcu_preempt20:50:253
1575599375,5cyclictest41-21ksoftirqd/322:45:003
15755993732,3cyclictest41-21ksoftirqd/321:20:143
15755993731,4cyclictest41-21ksoftirqd/300:19:593
1575599372,9cyclictest41-21ksoftirqd/300:30:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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