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2024-11-22 - 17:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Fri Nov 22, 2024 12:45:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
133391232167,22phc2sys0-21swapper/307:06:463
183122206172,23sleep10-21swapper/107:08:021
182082205172,23sleep20-21swapper/207:06:402
182062205171,23sleep00-21swapper/007:06:380
18467210364,30sleep20-21swapper/207:10:012
1333918362,11phc2sys0-21swapper/307:10:023
1875899679,17cyclictest11832-21df_abs10:20:140
1875899669,17cyclictest8063-21cpuspeed_turbos11:20:120
73332630,2sleep00-21swapper/009:00:140
1875899639,12cyclictest30157-21sed10:55:270
1875899639,12cyclictest30157-21sed10:55:270
1875899639,12cyclictest22582-21mailstats10:40:300
1875899628,12cyclictest16488-21date09:20:010
239542610,4sleep20-21swapper/207:20:152
1875899619,11cyclictest2689-21df_abs08:50:160
4142600,3sleep21876099cyclictest11:03:552
1875899609,11cyclictest32349-21sed09:55:120
1875899608,12cyclictest28563-21latency08:35:220
1875899608,12cyclictest10816-21awk10:15:270
120422600,3sleep2311rcuc/209:10:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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