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2024-08-14 - 20:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Wed Aug 14, 2024 12:46:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1235911730,6ptp4l401ktimersoftd/307:06:563
91192162139,10sleep20-21swapper/207:07:272
576981230,48rtkit-daemon29239-21apache207:09:231
9612999987,7cyclictest33-21ksoftirqd/207:45:122
9612999987,7cyclictest33-21ksoftirqd/207:45:122
9612999081,5cyclictest33-21ksoftirqd/207:15:132
9610998773,7cyclictest9-21ksoftirqd/007:35:100
9612998270,6cyclictest33-21ksoftirqd/210:15:092
9610998134,5cyclictest9-21ksoftirqd/008:20:270
9610997864,8cyclictest9-21ksoftirqd/012:20:120
9610997765,6cyclictest9-21ksoftirqd/009:55:120
961399768,21cyclictest24938-21latency_hist11:10:003
9610997564,6cyclictest9-21ksoftirqd/011:05:130
9610997562,7cyclictest9-21ksoftirqd/008:25:120
9610997463,7cyclictest9-21ksoftirqd/012:15:120
9610997463,7cyclictest9-21ksoftirqd/008:35:120
9610997462,7cyclictest9-21ksoftirqd/012:10:100
9610997462,7cyclictest9-21ksoftirqd/012:10:100
9610997462,7cyclictest9-21ksoftirqd/010:25:130
9612997359,8cyclictest33-21ksoftirqd/211:55:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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