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2025-04-02 - 04:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot2.osadl.org (updated Wed Apr 02, 2025 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
153042241196,34sleep30-21swapper/319:07:593
151332206172,23sleep20-21swapper/219:05:452
153022204173,20sleep10-21swapper/119:07:571
152232204171,22sleep00-21swapper/019:06:550
229821500,1sleep10-21swapper/119:50:011
137291810,1ptp4l29493-21apt-get23:35:143
31032660,3sleep00-21swapper/023:50:130
137291610,1ptp4l401ktimersoftd/319:55:393
244242570,1sleep00-21swapper/020:40:250
137291560,1ptp4l401ktimersoftd/300:02:353
15754995223,4cyclictest33-21ksoftirqd/223:20:192
137291510,1ptp4l401ktimersoftd/323:21:483
137291510,1ptp4l401ktimersoftd/323:01:383
137291510,1ptp4l401ktimersoftd/320:20:173
137291510,1ptp4l401ktimersoftd/320:20:173
250742480,2sleep30-21swapper/319:30:013
103652470,2sleep30-21swapper/320:10:123
1575599461,3cyclictest121rcu_preempt23:35:003
1575499442,7cyclictest33-21ksoftirqd/220:35:132
137291440,0ptp4l401ktimersoftd/323:49:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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