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2024-11-22 - 10:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Fri Nov 22, 2024 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
133391206148,47phc2sys0-21swapper/319:09:363
26792205173,21sleep20-21swapper/219:06:552
25882205172,22sleep10-21swapper/119:05:411
27552203170,22sleep00-21swapper/019:07:490
1884021690,8sleep3321299cyclictest23:05:123
1088321550,6sleep0320999cyclictest21:40:200
3210996623,9cyclictest25-21ksoftirqd/119:55:161
3210996424,8cyclictest25-21ksoftirqd/121:50:281
3210996323,8cyclictest25-21ksoftirqd/119:20:011
3210996322,9cyclictest25-21ksoftirqd/123:15:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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