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2024-07-16 - 08:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot2.osadl.org (updated Mon Jul 15, 2024 12:46:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1235911130,4ptp4l401ktimersoftd/307:07:253
123591870,2ptp4l401ktimersoftd/311:44:353
57698850,15rtkit-daemon0-21swapper/007:05:570
123591830,11ptp4l0-21swapper/309:22:143
123591830,11ptp4l0-21swapper/309:22:143
3049999761,26cyclictest7621-21cat08:39:080
3050199704,12cyclictest6868-21gunzip10:50:322
3050199702,12cyclictest583-21polkitd08:40:022
230362700,5sleep023038-21switchtime08:00:390
3050199683,18cyclictest27904-21latency_hist09:20:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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