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2024-11-22 - 16:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot1.osadl.org (updated Fri Nov 22, 2024 12:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1166911620,16ptp4l0-21swapper/107:08:151
1166911540,15ptp4l0-21swapper/007:09:180
858621420,7sleep31669499cyclictest10:20:293
1166911410,17ptp4l0-21swapper/207:07:082
1166911310,16ptp4l0-21swapper/307:07:103
116691700,2ptp4l0-21swapper/111:25:191
116691650,2ptp4l0-21swapper/108:35:201
116691650,2ptp4l0-21swapper/107:16:191
116691640,4ptp4l5557-21apt-get07:55:141
116691640,4ptp4l29879-21sed12:15:282
116691640,4ptp4l29879-21sed12:15:282
116691630,2ptp4l0-21swapper/009:35:280
116691620,4ptp4l17299-21hddtemp_smartct07:10:161
116691620,2ptp4l0-21swapper/111:15:201
138142600,5sleep113812-21tune2fs09:20:171
138142600,5sleep113812-21tune2fs09:20:171
116691600,5ptp4l13631-21sed08:10:211
116691600,1ptp4l0-21swapper/111:10:291
116691590,3ptp4l21886-21df_abs12:00:130
116691590,2ptp4l0-21swapper/111:44:071
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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