You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-07-16 - 08:17
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Mon Jul 15, 2024 12:46:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1176911710,15ptp4l0-21swapper/207:06:152
1176911630,16ptp4l0-21swapper/307:07:213
1176911600,15ptp4l0-21swapper/107:08:071
2966121550,7sleep11929099cyclictest09:45:291
1176911550,42ptp4l0-21swapper/007:05:070
1176911130,12ptp4l0-21swapper/007:10:020
407821000,8sleep31929299cyclictest11:06:453
222872950,4sleep2321ktimersoftd/208:25:112
222882790,8sleep01928999cyclictest11:45:330
222882790,8sleep01928999cyclictest11:45:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional