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2024-11-22 - 10:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot1.osadl.org (updated Fri Nov 22, 2024 00:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1166911960,12ptp4l33-21ksoftirqd/219:09:532
1166911960,12ptp4l33-21ksoftirqd/219:09:532
2414421770,8sleep3655299cyclictest23:15:153
1166911590,14ptp4l0-21swapper/019:07:480
1166911590,14ptp4l0-21swapper/019:07:470
1166911550,60ptp4l0-21swapper/119:06:381
1166911550,60ptp4l0-21swapper/119:06:381
1166911120,12ptp4l41-21ksoftirqd/319:05:323
1166911120,12ptp4l41-21ksoftirqd/319:05:313
1166911030,9ptp4l0-21swapper/119:10:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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