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2024-11-22 - 16:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot0.osadl.org (updated Fri Nov 22, 2024 12:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
973699240,6cyclictest7005-21latency_hist09:00:020
974599204,15cyclictest28-21ksoftirqd/209:39:052
974099201,3cyclictest4530-21H212:26:331
9740992011,8cyclictest0-21swapper/108:19:111
974099200,3cyclictest0-21swapper/107:43:551
974599193,1cyclictest31488-21cron10:45:012
9745991917,1cyclictest26283-21cat09:30:242
9745991917,1cyclictest0-21swapper/207:40:422
9745991915,3cyclictest4538-21H212:26:332
9745991915,3cyclictest0-21swapper/207:45:132
974599190,18cyclictest823-21systemd-network08:11:422
974599190,16cyclictest4593-21H212:26:332
974099193,15cyclictest0-21swapper/108:00:201
974099192,16cyclictest970-21dbus-daemon10:15:201
974099192,16cyclictest23585-21nfsd411:25:171
974099190,16cyclictest4523-21H212:26:331
973699192,2cyclictest20058-21missed_timers07:25:180
9736991917,1cyclictest9-21ksoftirqd/007:20:000
9736991914,1cyclictest0-21swapper/011:30:180
973699190,2cyclictest4528-21H212:26:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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