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2025-04-02 - 08:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Wed Apr 02, 2025 00:45:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2891699240,18cyclictest0-21swapper/122:55:141
2891699230,21cyclictest4523-21H212:26:331
28914992313,4cyclictest0-21swapper/022:05:010
28916992214,7cyclictest4528-21H212:26:331
28916992213,8cyclictest4593-21H212:26:331
28916992211,6cyclictest21946-21latency_hist23:15:001
2891699220,2cyclictest13944-21cut19:40:151
2891699220,2cyclictest1166-21grep19:15:211
2891699220,21cyclictest6349-21tr20:30:101
2891699220,20cyclictest0-21swapper/100:35:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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