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2024-11-22 - 10:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Fri Nov 22, 2024 00:45:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2921599230,18cyclictest0-21swapper/200:10:192
2921199236,2cyclictest10124-21mii-tool21:25:161
2921599210,17cyclictest0-21swapper/220:28:262
2921199210,19cyclictest13424-21fschecks_time20:35:141
2921099210,3cyclictest0-21swapper/020:17:360
2921599200,13cyclictest0-21swapper/223:34:202
2921599190,18cyclictest14044-21nfsd420:35:172
29211991915,3cyclictest0-21swapper/121:44:021
2921199190,15cyclictest0-21swapper/119:25:141
29210991913,3cyclictest0-21swapper/000:27:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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