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2024-07-16 - 08:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackdslot0.osadl.org (updated Mon Jul 15, 2024 12:45:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
267799428427,1cyclictest3805-21kworker/u16:208:34:430
268799417416,1cyclictest0-21swapper/207:29:032
268799396392,4cyclictest0-21swapper/212:22:022
268799394392,0cyclictest0-21swapper/211:18:022
268799384382,2cyclictest0-21swapper/210:41:022
268799379377,2cyclictest0-21swapper/208:33:032
268799375375,0cyclictest0-21swapper/211:45:012
267799323321,2cyclictest0-21swapper/007:29:030
268299312311,1cyclictest542-21kworker/1:107:29:021
268299299297,1cyclictest0-21swapper/107:20:581
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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