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2025-04-03 - 15:33

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #c, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8s.osadl.org (updated Thu Apr 03, 2025 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
114091630,8ptp4l0-21swapper/119:09:421
3213026151,6sleep30-21swapper/319:09:503
114091610,5ptp4l0-21swapper/419:08:564
284872600,0sleep00-21swapper/000:10:120
284872600,0sleep00-21swapper/000:10:120
114091580,5ptp4l0-21swapper/519:07:275
324772570,0sleep70-21swapper/721:20:147
3192425747,6sleep70-21swapper/719:07:137
156082570,0sleep30-21swapper/323:10:003
114091570,5ptp4l0-21swapper/019:08:090
3198325343,6sleep20-21swapper/219:07:562
3196924938,6sleep60-21swapper/619:07:436
114091330,0ptp4l0-21swapper/120:10:221
114091320,0ptp4l0-21swapper/023:47:430
114091310,0ptp4l0-21swapper/620:50:166
114091310,0ptp4l0-21swapper/521:31:555
114091310,0ptp4l0-21swapper/521:31:555
114091310,0ptp4l0-21swapper/421:46:574
114091310,0ptp4l0-21swapper/121:30:071
114091310,0ptp4l0-21swapper/121:30:061
114091300,0ptp4l0-21swapper/623:42:536
114091300,0ptp4l0-21swapper/121:18:461
114091290,0ptp4l0-21swapper/621:55:496
114091290,0ptp4l0-21swapper/600:15:536
114091290,0ptp4l0-21swapper/600:15:526
114091290,0ptp4l0-21swapper/523:27:385
114091290,0ptp4l0-21swapper/522:23:415
114091290,0ptp4l0-21swapper/122:47:031
114091290,0ptp4l0-21swapper/121:27:161
114091280,3ptp4l0-21swapper/621:32:196
114091280,3ptp4l0-21swapper/621:32:196
114091280,0ptp4l0-21swapper/521:24:355
114091280,0ptp4l0-21swapper/519:37:165
114091280,0ptp4l0-21swapper/221:36:542
114091280,0ptp4l0-21swapper/123:13:331
114091280,0ptp4l0-21swapper/121:21:381
114091280,0ptp4l0-21swapper/021:21:070
114091270,2ptp4l0-21swapper/120:09:411
114091270,0ptp4l0-21swapper/523:35:055
114091270,0ptp4l0-21swapper/523:21:225
114091270,0ptp4l0-21swapper/521:43:105
114091270,0ptp4l0-21swapper/500:20:185
114091270,0ptp4l0-21swapper/500:17:305
114091270,0ptp4l0-21swapper/500:17:305
114091270,0ptp4l0-21swapper/222:56:222
114091270,0ptp4l0-21swapper/123:18:051
114091270,0ptp4l0-21swapper/123:06:241
114091270,0ptp4l0-21swapper/122:40:171
114091270,0ptp4l0-21swapper/121:48:281
114091270,0ptp4l0-21swapper/100:27:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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