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2024-07-16 - 06:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackcslot8.osadl.org (updated Mon Jul 15, 2024 12:49:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
529099495493,1cyclictest11287-21lspci08:28:452
541299356156,0cyclictest185-21ksoftirqd/2811:33:5021
537799337140,166cyclictest151rcu_preempt11:06:5013
537799337140,166cyclictest151rcu_preempt11:06:5013
23762321313,6sleep300-21swapper/3007:05:2224
54129917756,120cyclictest0-21swapper/2811:20:3421
54129917756,120cyclictest0-21swapper/2811:20:3321
54129916414,148cyclictest151rcu_preempt11:27:2721
54129916414,148cyclictest151rcu_preempt11:27:2721
53659916126,100cyclictest0-21swapper/1811:35:1610
53659916026,118cyclictest0-21swapper/1809:35:0110
53659915826,85cyclictest0-21swapper/1808:29:5010
54129915435,65cyclictest0-21swapper/2811:55:0121
231191154149,3phc2sys0-21swapper/207:09:4712
53659915319,109cyclictest0-21swapper/1808:35:0910
53659915220,108cyclictest0-21swapper/1810:14:4110
53659915220,108cyclictest0-21swapper/1810:14:4010
54129915131,96cyclictest0-21swapper/2809:15:2321
54129914959,42cyclictest0-21swapper/2807:24:3721
52739914996,53cyclictest64-21ksoftirqd/809:46:5830
52739914927,120cyclictest151rcu_preempt11:56:3430
5425991450,86cyclictest0-21swapper/3112:00:3725
53299914425,117cyclictest0-21swapper/1410:45:316
53299914425,117cyclictest0-21swapper/1410:45:306
53299914325,92cyclictest0-21swapper/1410:05:576
53299914325,92cyclictest0-21swapper/1410:05:576
53299914325,117cyclictest0-21swapper/1411:36:496
52739914317,102cyclictest0-21swapper/809:44:1730
53899914233,108cyclictest0-21swapper/2311:45:3216
53299914225,87cyclictest0-21swapper/1412:04:296
53299914225,102cyclictest0-21swapper/1412:22:466
54129914123,72cyclictest0-21swapper/2811:19:4421
54129914123,72cyclictest0-21swapper/2811:19:4321
5412991410,84cyclictest0-21swapper/2810:54:0621
5412991410,84cyclictest0-21swapper/2810:54:0521
5397991410,84cyclictest0-21swapper/2509:50:3818
53479914140,68cyclictest151rcu_preempt08:09:188
53299914125,85cyclictest0-21swapper/1412:07:036
54259914039,66cyclictest0-21swapper/3109:55:3325
54259914027,68cyclictest0-21swapper/3110:31:2225
54259914027,68cyclictest0-21swapper/3110:31:2225
53479914065,31cyclictest151rcu_preempt07:45:158
53299914025,72cyclictest0-21swapper/1411:00:296
53299914025,72cyclictest0-21swapper/1411:00:286
52739914022,73cyclictest0-21swapper/810:52:4030
52739914022,73cyclictest0-21swapper/810:52:3930
54129913949,58cyclictest0-21swapper/2810:05:3021
54129913949,58cyclictest0-21swapper/2810:05:3021
53479913913,78cyclictest0-21swapper/1608:50:268
54259913828,71cyclictest0-21swapper/3110:53:1725
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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