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2024-11-22 - 17:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackcslot8.osadl.org (updated Fri Nov 22, 2024 12:49:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31083993029,290cyclictest0-21swapper/512:08:2827
31083993029,290cyclictest0-21swapper/512:08:2827
3108399300102,1cyclictest151rcu_preempt12:35:2927
3108399300102,1cyclictest151rcu_preempt12:35:2827
310749928881,9cyclictest40-21ksoftirqd/412:15:0126
310749928881,9cyclictest40-21ksoftirqd/412:15:0126
2482912310,218ptp4l0-21swapper/107:05:141
2482912310,218ptp4l0-21swapper/107:05:141
310749917422,96cyclictest0-21swapper/411:15:2126
310839916310,92cyclictest0-21swapper/511:35:5227
312299915790,1cyclictest151rcu_preempt10:15:2117
31174991530,91cyclictest0-21swapper/1707:15:189
31174991530,91cyclictest0-21swapper/1707:15:189
311649914628,46cyclictest0-21swapper/1610:25:198
31174991440,86cyclictest0-21swapper/1708:50:259
311649914224,118cyclictest0-21swapper/1612:15:108
311649914224,118cyclictest0-21swapper/1612:15:098
31164991420,86cyclictest0-21swapper/1609:50:038
311749914155,77cyclictest0-21swapper/1707:24:559
311749914155,77cyclictest0-21swapper/1707:24:549
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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