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2025-04-02 - 08:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot8.osadl.org (updated Wed Apr 02, 2025 00:50:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
63869923537,1cyclictest151rcu_preempt21:57:4028
63869923537,1cyclictest151rcu_preempt21:57:4028
2482912320,224ptp4l0-21swapper/119:07:271
63519922827,198cyclictest151rcu_preempt23:14:001
329891228220,6phc2sys0-21swapper/219:05:1612
64799918514,169cyclictest0-21swapper/2521:50:1818
64799918514,169cyclictest0-21swapper/2521:50:1818
64799918116,113cyclictest0-21swapper/2523:55:2818
64559917433,94cyclictest0-21swapper/2021:05:2013
64559917433,94cyclictest0-21swapper/2021:05:1913
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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