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2024-11-22 - 10:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Fri Nov 22, 2024 00:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28424982293251,28sleep10-21swapper/119:06:061
28427452289247,28sleep00-21swapper/019:08:460
30071462510,4sleep10-21swapper/123:34:201
29901052470,7sleep00-21swapper/023:11:440
28759162450,2sleep00-21swapper/020:30:170
113399440,3rtkit-daemon0-21swapper/119:38:331
113399420,3rtkit-daemon0-21swapper/119:40:381
113399390,3rtkit-daemon0-21swapper/122:16:301
113399390,3rtkit-daemon0-21swapper/119:46:501
113399380,3rtkit-daemon0-21swapper/123:12:391
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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