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2025-04-02 - 08:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot4.osadl.org (updated Wed Apr 02, 2025 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
63129599488485,2cyclictest834783-21turbostat00:40:001
63129599444441,2cyclictest775456-21turbostat23:20:001
63129599430409,19cyclictest811679-21turbostat00:10:001
63129599424421,2cyclictest670994-21turbostat20:59:541
63129599410407,2cyclictest767273-21turbostat23:10:001
63129599371369,1cyclictest797199-21turbostat23:54:551
63129599352346,4cyclictest660236-21turbostat20:25:001
63129599351347,3cyclictest815836-21turbostat00:15:001
63129599345343,1cyclictest670994-21turbostat20:55:001
63129599323321,1cyclictest633173-21turbostat19:15:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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