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2024-07-16 - 08:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rackcslot2.osadl.org (updated Mon Jul 15, 2024 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2974426955,9sleep10-21swapper/107:02:291
2830726445,3sleep00-21swapper/006:59:330
30106991816,1cyclictest10103-21ls10:24:521
46642170,1sleep00-21swapper/010:19:110
30106991710,7cyclictest0-21swapper/107:40:561
30106991710,6cyclictest18120-21sleep09:54:021
30105991715,1cyclictest195422sleep007:57:440
30105991715,1cyclictest1880-21ls11:39:460
30106991615,1cyclictest0-21swapper/110:15:281
30106991615,0cyclictest1374-21ssh10:56:511
30106991610,6cyclictest0-21swapper/109:07:321
30106991610,6cyclictest0-21swapper/107:58:591
30106991610,5cyclictest0-21swapper/111:35:481
30106991610,0cyclictest0-21swapper/109:09:471
30106991610,0cyclictest0-21swapper/108:24:561
30105991614,1cyclictest6627-21ls07:24:470
30105991611,5cyclictest28490-21kworker/0:211:21:380
30105991611,5cyclictest28490-21kworker/0:210:42:420
30105991611,5cyclictest28490-21kworker/0:209:50:260
30105991611,5cyclictest28490-21kworker/0:209:28:420
30105991611,5cyclictest2631-21kworker/0:012:05:540
30105991610,6cyclictest0-21swapper/009:59:220
30105991610,5cyclictest28490-21kworker/0:209:23:060
30106991515,0cyclictest0-21swapper/111:34:191
30106991515,0cyclictest0-21swapper/109:01:271
30106991515,0cyclictest0-21swapper/108:02:591
30106991511,3cyclictest0-21swapper/107:20:161
30106991510,5cyclictest0-21swapper/111:44:201
30106991510,5cyclictest0-21swapper/110:02:241
30106991510,5cyclictest0-21swapper/109:56:241
30106991510,5cyclictest0-21swapper/109:38:441
30106991510,5cyclictest0-21swapper/108:53:161
30106991510,5cyclictest0-21swapper/108:10:101
30106991510,5cyclictest0-21swapper/107:44:521
30106991510,5cyclictest0-21swapper/107:39:121
30106991510,5cyclictest0-21swapper/107:31:561
30106991510,5cyclictest0-21swapper/107:27:041
30106991510,1cyclictest0-21swapper/109:15:201
30106991510,0cyclictest0-21swapper/111:18:361
30106991510,0cyclictest0-21swapper/108:19:211
30105991511,4cyclictest28490-21kworker/0:211:18:100
30105991510,5cyclictest28490-21kworker/0:211:27:220
30105991510,5cyclictest28490-21kworker/0:210:54:140
30105991510,5cyclictest28490-21kworker/0:209:40:300
30105991510,5cyclictest28490-21kworker/0:209:29:380
30105991510,5cyclictest28490-21kworker/0:208:43:100
30105991510,5cyclictest2631-21kworker/0:012:20:300
30105991510,5cyclictest2631-21kworker/0:012:11:340
30105991510,5cyclictest2631-21kworker/0:011:57:500
30105991510,0cyclictest0-21swapper/009:08:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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