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2024-11-22 - 17:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot2.osadl.org (updated Fri Nov 22, 2024 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3250227347,21sleep00-21swapper/007:06:360
3262226854,8sleep10-21swapper/107:07:511
97102630,0sleep00-21swapper/011:02:420
301362620,0sleep00-21swapper/009:27:270
502992827,0cyclictest0-21swapper/110:04:281
501992821,6cyclictest0-21swapper/009:09:450
502992720,5cyclictest10407-21apache211:33:561
501992725,2cyclictest0-21swapper/010:53:270
502992610,1cyclictest0-21swapper/111:59:581
502992610,0cyclictest0-21swapper/111:17:391
50299260,25cyclictest0-21swapper/110:27:531
50299260,0cyclictest0-21swapper/111:07:251
501992625,1cyclictest0-21swapper/010:48:100
501992616,8cyclictest10407-21apache211:10:130
502992524,1cyclictest0-21swapper/107:53:051
502992520,4cyclictest10429-21apache212:29:481
50299250,2cyclictest25917-21ssh11:22:301
501992517,6cyclictest10407-21apache210:04:280
501992510,5cyclictest0-21swapper/009:04:410
502992423,0cyclictest0-21swapper/110:33:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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