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2025-04-02 - 08:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Wed Apr 02, 2025 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1678826856,8sleep00-21swapper/019:06:430
1666826855,9sleep10-21swapper/119:05:271
201312630,0sleep00-21swapper/023:00:060
17144993434,0cyclictest7-21ksoftirqd/022:18:320
17144993410,0cyclictest0-21swapper/022:03:000
17144993210,2cyclictest0-21swapper/023:31:390
17144993210,2cyclictest0-21swapper/022:47:430
1714599310,30cyclictest11815-21kworker/u4:123:44:261
17145993030,0cyclictest0-21swapper/121:11:171
1714599300,28cyclictest0-21swapper/122:25:451
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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