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2024-07-16 - 08:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot2.osadl.org (updated Mon Jul 15, 2024 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2974426955,9sleep10-21swapper/107:02:291
2830726445,3sleep00-21swapper/006:59:330
30106991816,1cyclictest10103-21ls10:24:521
46642170,1sleep00-21swapper/010:19:110
30106991710,7cyclictest0-21swapper/107:40:561
30106991710,6cyclictest18120-21sleep09:54:021
30105991715,1cyclictest195422sleep007:57:440
30105991715,1cyclictest1880-21ls11:39:460
30106991615,1cyclictest0-21swapper/110:15:281
30106991615,0cyclictest1374-21ssh10:56:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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