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2025-04-02 - 04:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot1.osadl.org (updated Wed Apr 02, 2025 01:27:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,9101
"cycles":100000000,9100
"load":"idle",9099
"condition":{9098
"clock":"3467"9096
"family":"x86",9095
"vendor":"Intel",9094
"processor":{9092
"dataset":"2024-01-08T16:48:10+01:00"9090
"origin":"2024-01-08T12:43:21+01:00",9089
"timestamps":{9088
"granularity":"microseconds"9086
"maxima":[9072
"cores":[3844
"latency":{3843
"hostname":"rackcslot1.osadl.org"3841
"system":{3840
"version":"1.0",3837
"format":{3836
"patches":[3824
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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