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2025-04-02 - 06:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rackcslot1.osadl.org (updated Wed Apr 02, 2025 01:27:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,9101
"cycles":100000000,9100
"load":"idle",9099
"condition":{9098
"clock":"3467"9096
"family":"x86",9095
"vendor":"Intel",9094
"processor":{9092
"dataset":"2024-01-08T16:48:10+01:00"9090
"origin":"2024-01-08T12:43:21+01:00",9089
"timestamps":{9088
"granularity":"microseconds"9086
"maxima":[9072
"cores":[3844
"latency":{3843
"hostname":"rackcslot1.osadl.org"3841
"system":{3840
"version":"1.0",3837
"format":{3836
"patches":[3824
206752700,2sleep30-21swapper/35
254962610,1sleep90-21swapper/911
114382590,1sleep00-21swapper/00
883999306,18cyclictest0-21swapper/00
883999306,18cyclictest0-21swapper/00
887499245,13cyclictest0-21swapper/68
886999245,14cyclictest0-21swapper/57
885699244,14cyclictest0-21swapper/35
885699244,14cyclictest0-21swapper/35
888799234,14cyclictest0-21swapper/810
885699223,13cyclictest0-21swapper/35
887499214,13cyclictest0-21swapper/68
885299214,12cyclictest0-21swapper/24
885299214,12cyclictest0-21swapper/24
885299213,13cyclictest0-21swapper/24
889499204,11cyclictest0-21swapper/911
889499203,14cyclictest0-21swapper/911
889499203,12cyclictest0-21swapper/911
889499203,11cyclictest0-21swapper/911
889499200,12cyclictest0-21swapper/911
887499204,11cyclictest0-21swapper/68
887499204,11cyclictest0-21swapper/68
887499203,12cyclictest0-21swapper/68
885299203,12cyclictest0-21swapper/24
8839992019,1cyclictest3-21ksoftirqd/00
890499194,11cyclictest0-21swapper/113
889499194,12cyclictest0-21swapper/911
889499194,11cyclictest0-21swapper/911
889499193,12cyclictest0-21swapper/911
889499190,11cyclictest0-21swapper/911
888799191,11cyclictest0-21swapper/810
8881991915,3cyclictest0-21swapper/79
885699194,12cyclictest0-21swapper/35
885699194,10cyclictest0-21swapper/35
885699193,12cyclictest0-21swapper/35
885699193,11cyclictest0-21swapper/35
885699193,10cyclictest0-21swapper/35
885299194,11cyclictest0-21swapper/24
883999194,12cyclictest0-21swapper/00
883999194,12cyclictest0-21swapper/00
883999194,10cyclictest0-21swapper/00
883999193,10cyclictest0-21swapper/00
75662190,1sleep00-21swapper/00
890499184,10cyclictest0-21swapper/113
890499183,10cyclictest0-21swapper/113
889899180,17cyclictest0-21swapper/102
889499180,2cyclictest0-21swapper/911
889499180,12cyclictest0-21swapper/911
889499180,12cyclictest0-21swapper/911
888799184,10cyclictest0-21swapper/810
888799183,10cyclictest0-21swapper/810
887499184,10cyclictest0-21swapper/68
8874991814,3cyclictest0-21swapper/68
886999181,12cyclictest0-21swapper/57
885699183,11cyclictest0-21swapper/35
885699183,11cyclictest0-21swapper/35
885699183,11cyclictest0-21swapper/35
883999183,11cyclictest0-21swapper/00
890499172,12cyclictest0-21swapper/113
889499177,3cyclictest0-21swapper/911
889499173,10cyclictest0-21swapper/911
889499170,3cyclictest0-21swapper/911
889499170,2cyclictest0-21swapper/911
889499170,16cyclictest25619-21ssh11
889499170,16cyclictest25619-21ssh11
888799172,11cyclictest0-21swapper/810
885699173,10cyclictest0-21swapper/35
885699173,10cyclictest0-21swapper/35
885299172,11cyclictest0-21swapper/24
883999173,10cyclictest0-21swapper/00
883999171,12cyclictest0-21swapper/00
883999171,12cyclictest0-21swapper/00
37522170,1sleep60-21swapper/68
890499163,10cyclictest0-21swapper/113
890499160,15cyclictest0-21swapper/113
890499160,15cyclictest0-21swapper/113
890499160,15cyclictest0-21swapper/113
889499162,10cyclictest0-21swapper/911
889499160,8cyclictest0-21swapper/911
889499160,15cyclictest0-21swapper/911
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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