You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-03-12 - 05:37
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Wed Mar 12, 2025 00:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
738421520,0sleep100-21swapper/1000:40:192
283921360,6sleep1313099cyclictest22:35:321
24602117103,8sleep120-21swapper/1219:14:064
2628211691,19sleep130-21swapper/1319:16:315
16332115104,6sleep40-21swapper/419:12:5410
1216721080,1sleep812164-21sshd21:33:2014
2501210593,8sleep150-21swapper/1519:14:417
178221030,7sleep3313399cyclictest22:02:569
2703210287,11sleep00-21swapper/019:16:510
2312421010,5sleep14314999cyclictest21:50:336
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional