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2024-11-22 - 17:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackcslot0.osadl.org (updated Fri Nov 22, 2024 00:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2400221440,4sleep71319399cyclictest22:24:1313
2400221440,4sleep71319399cyclictest22:24:1313
125222118103,11sleep60-21swapper/619:13:0112
12700211493,15sleep20-21swapper/219:14:498
12458211393,13sleep110-21swapper/1119:12:173
3179521100,1sleep110-21swapper/1121:54:033
2194321090,2sleep666-21ksoftirqd/623:56:1212
12636210992,10sleep100-21swapper/1019:14:412
12433210994,11sleep70-21swapper/719:11:5713
12638210692,10sleep120-21swapper/1219:14:434
12408210391,8sleep40-21swapper/419:11:3810
12407210391,8sleep30-21swapper/319:11:379
1880321000,1sleep30-21swapper/323:33:579
275922990,1sleep120-21swapper/1222:30:274
275922990,1sleep120-21swapper/1222:30:274
242402990,2sleep666-21ksoftirqd/623:01:5412
136032960,0sleep150-21swapper/1522:38:477
1258029570,19sleep80-21swapper/819:13:5114
115622950,1sleep30-21swapper/322:33:149
115622950,1sleep30-21swapper/322:33:149
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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