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2024-07-16 - 08:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Mon Jul 15, 2024 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
48282142121,14sleep140-21swapper/1419:13:086
48282142121,14sleep140-21swapper/1419:13:086
47832129107,17sleep40-21swapper/419:12:2610
47832129107,17sleep40-21swapper/419:12:2610
48852119102,13sleep20-21swapper/219:13:128
48852119102,13sleep20-21swapper/219:13:128
47712119103,11sleep110-21swapper/1119:12:173
47712119103,11sleep110-21swapper/1119:12:173
824521150,0sleep20-21swapper/222:05:088
3184421130,6sleep2534099cyclictest00:07:548
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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