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2025-04-02 - 08:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackcslot0.osadl.org (updated Wed Apr 02, 2025 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2821421420,5sleep02083799cyclictest00:07:450
2821421420,5sleep02083799cyclictest00:07:450
200672140116,19sleep60-21swapper/619:14:3012
20035212490,30sleep90-21swapper/919:14:0115
201372116103,8sleep20-21swapper/219:15:308
19283211491,19sleep100-21swapper/1019:13:132
20079211392,13sleep10-21swapper/119:14:411
19340211293,13sleep140-21swapper/1419:13:336
19232211183,23sleep50-21swapper/519:12:5211
20090210593,8sleep70-21swapper/719:14:4713
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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