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2024-09-01 - 01:00

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #b, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackbslot8s (updated Sat Aug 31, 2024 12:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41780992131117,9sleep50-21swapper/507:09:045
41779992128104,9sleep00-21swapper/007:07:390
417841999127126,1cyclictest2493696-21kworker/6:209:18:156
41760472126111,10sleep60-21swapper/607:05:046
417840299125125,0cyclictest0-21swapper/212:25:232
41780742122108,9sleep70-21swapper/707:08:427
41780662122107,10sleep20-21swapper/207:08:382
41780142122108,9sleep40-21swapper/407:07:514
41778432119105,9sleep10-21swapper/107:05:241
417840299115115,0cyclictest0-21swapper/209:18:162
41778542115101,9sleep30-21swapper/307:05:343
4178422991030,100cyclictest0-21swapper/710:10:507
417840799103100,3cyclictest573-21snmpd10:48:033
4178422991020,100cyclictest0-21swapper/712:12:597
4178422991020,100cyclictest0-21swapper/708:52:297
41784079910299,3cyclictest573-21snmpd12:09:233
41783989910298,0cyclictest573-21snmpd12:30:001
41784199910199,2cyclictest2493696-21kworker/6:212:05:076
41784199910199,1cyclictest573-21snmpd07:20:066
41784199910199,1cyclictest2493696-21kworker/6:212:10:216
417841999101100,1cyclictest2493696-21kworker/6:212:16:336
417841999101100,1cyclictest2493696-21kworker/6:211:58:346
417841999101100,1cyclictest2493696-21kworker/6:211:51:236
417841999101100,1cyclictest2493696-21kworker/6:211:48:436
417841999101100,1cyclictest2493696-21kworker/6:211:43:016
417841999101100,1cyclictest2493696-21kworker/6:211:38:036
417841999101100,1cyclictest2493696-21kworker/6:211:30:486
417841999101100,1cyclictest2493696-21kworker/6:211:27:176
417841999101100,1cyclictest2493696-21kworker/6:211:17:176
417841999101100,1cyclictest2493696-21kworker/6:211:10:116
417841999101100,1cyclictest2493696-21kworker/6:211:08:556
417841999101100,1cyclictest2493696-21kworker/6:211:00:106
417841999101100,1cyclictest2493696-21kworker/6:210:45:336
417841999101100,1cyclictest2493696-21kworker/6:210:44:006
417841999101100,1cyclictest2493696-21kworker/6:210:28:596
417841999101100,1cyclictest2493696-21kworker/6:210:20:076
417841999101100,1cyclictest2493696-21kworker/6:210:19:246
417841999101100,1cyclictest2493696-21kworker/6:209:56:076
417841999101100,1cyclictest2493696-21kworker/6:209:44:316
417841999101100,1cyclictest2493696-21kworker/6:209:36:536
417841999101100,1cyclictest2493696-21kworker/6:209:31:456
417841999101100,1cyclictest2493696-21kworker/6:209:25:026
417841999101100,1cyclictest2493696-21kworker/6:209:21:416
417841999101100,1cyclictest2493696-21kworker/6:209:10:416
417841999101100,1cyclictest2493696-21kworker/6:208:05:146
41784159910199,2cyclictest573-21snmpd09:44:465
41784159910198,2cyclictest573-21snmpd11:51:145
4178415991010,100cyclictest0-21swapper/512:17:095
41784109910199,2cyclictest573-21snmpd11:26:054
417841099101100,1cyclictest573-21snmpd09:33:014
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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