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2024-11-22 - 17:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rackbslot7.osadl.org (updated Fri Nov 22, 2024 12:44:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3156321050,4chrt31532-21apt-get08:15:032
1179021010,4sleep20-21swapper/211:44:552
1179021010,4sleep20-21swapper/211:44:552
941099905,39cyclictest24238-21apt-get12:05:132
43212900,6sleep30-21swapper/309:43:043
941099885,78cyclictest13401-21kworker/u8:209:25:022
941099885,78cyclictest13401-21kworker/u8:209:25:022
928628416,32sleep00-21swapper/007:09:340
9410998226,23cyclictest0-21swapper/210:19:342
9410998226,23cyclictest0-21swapper/210:19:342
9388998235,23cyclictest12-21ksoftirqd/007:44:360
9410998135,13cyclictest33-21ksoftirqd/211:22:042
9388997938,31cyclictest12-21ksoftirqd/008:25:000
90682796,51sleep10-21swapper/107:07:281
9410997854,15cyclictest28246-21fschecks_count08:04:542
9410997833,24cyclictest141rcu_preempt07:24:352
9410997750,19cyclictest17882-21timerandwakeup09:10:062
9410997735,18cyclictest141rcu_preempt09:19:362
9410997636,14cyclictest141rcu_preempt07:14:352
9388997647,18cyclictest28352-21unixbench_multi10:25:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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