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2025-04-02 - 08:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rackbslot1.osadl.org (updated Tue Apr 01, 2025 12:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
34694882207183,14sleep30-21swapper/307:09:453
34693012203179,14sleep10-21swapper/107:07:191
34692972197170,18sleep20-21swapper/207:07:162
34693952176153,14sleep00-21swapper/007:08:300
3469702996764,2cyclictest3605102-21kworker/u8:3+flush-179:009:45:010
3469702996259,2cyclictest3698861-21kworker/u8:0+events_unbound11:15:190
3469702996258,3cyclictest3698861-21kworker/u8:0+flush-179:011:30:010
3469702996258,3cyclictest3657612-21kworker/u8:1+flush-179:011:00:040
3469702996056,3cyclictest3606029-21ThreadPoolForeg07:45:020
3469702995956,2cyclictest3662676-21kworker/u8:3+flush-179:010:55:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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