You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-11-25 - 06:56

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #a, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  TI
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rackaslot5s.osadl.org (updated Mon Nov 25, 2024 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
811340,0rcu_preempt3-21ksoftirqd/023:19:580
811340,0rcu_preempt3-21ksoftirqd/021:42:410
811330,0rcu_preempt3-21ksoftirqd/023:09:130
811310,0rcu_preempt3-21ksoftirqd/021:50:350
811310,0rcu_preempt3-21ksoftirqd/021:26:180
811300,0rcu_preempt3-21ksoftirqd/022:05:350
811300,0rcu_preempt3-21ksoftirqd/021:13:230
811290,0rcu_preempt3-21ksoftirqd/021:21:520
811280,0rcu_preempt3-21ksoftirqd/023:31:020
811280,0rcu_preempt3-21ksoftirqd/022:51:360
811280,0rcu_preempt3-21ksoftirqd/021:16:570
811270,0rcu_preempt3-21ksoftirqd/023:06:230
811270,0rcu_preempt3-21ksoftirqd/023:06:230
811230,0rcu_preempt3-21ksoftirqd/023:48:300
811160,0rcu_preempt3-21ksoftirqd/022:42:040
811090,0rcu_preempt3-21ksoftirqd/021:58:410
811080,0rcu_preempt17588-21kworker/0:123:39:490
811040,0rcu_preempt3-21ksoftirqd/022:47:130
811030,0rcu_preempt3-21ksoftirqd/022:58:520
811030,0rcu_preempt3-21ksoftirqd/022:23:180
811010,0rcu_preempt3-21ksoftirqd/023:36:300
811010,0rcu_preempt3-21ksoftirqd/000:18:080
811000,0rcu_preempt3-21ksoftirqd/023:14:390
811000,0rcu_preempt3-21ksoftirqd/022:38:160
811000,0rcu_preempt3-21ksoftirqd/022:12:420
81990,0rcu_preempt3-21ksoftirqd/000:28:200
81980,0rcu_preempt3-21ksoftirqd/023:27:100
81980,0rcu_preempt3-21ksoftirqd/022:31:120
81980,0rcu_preempt3-21ksoftirqd/022:14:360
81980,0rcu_preempt3-21ksoftirqd/021:30:030
81980,0rcu_preempt3-21ksoftirqd/000:20:200
81980,0rcu_preempt3-21ksoftirqd/000:13:240
81970,0rcu_preempt30798-21kworker/0:121:53:450
81970,0rcu_preempt30798-21kworker/0:121:53:450
81820,0rcu_preempt54-21kswapd020:08:400
81810,0rcu_preempt3-21ksoftirqd/020:03:390
81800,0rcu_preempt3-21ksoftirqd/020:13:490
81800,0rcu_preempt3-21ksoftirqd/000:29:230
81790,0rcu_preempt3-21ksoftirqd/023:59:290
81790,0rcu_preempt3-21ksoftirqd/020:38:140
81790,0rcu_preempt3-21ksoftirqd/020:20:490
81790,0rcu_preempt3-21ksoftirqd/000:03:580
81780,0rcu_preempt3-21ksoftirqd/023:56:430
81780,0rcu_preempt3-21ksoftirqd/020:28:520
81760,0rcu_preempt3-21ksoftirqd/021:44:450
81760,0rcu_preempt3-21ksoftirqd/020:43:430
81760,0rcu_preempt3-21ksoftirqd/020:00:200
81760,0rcu_preempt3-21ksoftirqd/019:55:380
81760,0rcu_preempt3-21ksoftirqd/019:13:390
81760,0rcu_preempt3-21ksoftirqd/000:37:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional