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2024-11-22 - 16:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackaslot0.osadl.org (updated Fri Nov 22, 2024 12:44:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
229772840,1sleep11855699cyclictest12:06:351
264692590,1sleep026450-21sshd09:41:050
264692590,1sleep026450-21sshd09:41:050
326362580,0sleep20-21swapper/211:48:132
232842580,2sleep01855599cyclictest10:07:090
232842580,2sleep01855599cyclictest10:07:090
218342580,0sleep321825-21sshd10:13:333
313872570,6sleep031364-21sshd10:20:580
174952570,0sleep30-21swapper/311:03:003
303442560,0sleep00-21swapper/011:09:370
101192560,0sleep20-21swapper/212:35:452
204242550,1sleep120427-21id12:20:131
308142540,1sleep011248-21diskmemload09:25:070
295352540,1sleep129534-21sshd09:18:231
1802125330,19sleep20-21swapper/207:06:392
277822520,0sleep00-21swapper/010:10:410
1805125229,19sleep00-21swapper/007:07:010
136422520,0sleep113641-21sshd12:27:511
274452510,0sleep20-21swapper/209:44:322
274452510,0sleep20-21swapper/209:44:312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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