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2025-04-02 - 08:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack9slot6.osadl.org (updated Wed Apr 02, 2025 00:53:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3814:12:505033
36,14:12:125032
38,14:12:125031
24,14:12:125030
014:12:125026
0,14:12:125025
0,14:12:125024
0,14:12:125023
0,14:12:125022
0,14:12:125021
0,14:12:125020
0,14:12:125019
0,14:12:125018
0,14:12:125017
0,14:12:125016
0,14:12:125015
0,14:12:125014
0,14:12:125013
0,14:12:125012
0,14:12:125011
0,14:12:125010
0,14:12:125009
0,14:12:125008
0,14:12:125007
0,14:12:125006
0,14:12:125005
0,14:12:125004
0,14:12:125003
0,14:12:125002
0,14:12:125001
0,14:12:125000
0,14:12:124999
0,14:12:124998
0,14:12:124997
0,14:12:124996
0,14:12:124995
0,14:12:124994
0,14:12:124993
0,14:12:124992
0,14:12:124991
0,14:12:124990
0,14:12:124989
0,14:12:124988
0,14:12:124987
0,14:12:124986
0,14:12:124985
0,14:12:124984
0,14:12:124983
0,14:12:124982
0,14:12:124981
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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