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2025-04-03 - 15:45

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot7s.osadl.org (updated Thu Apr 03, 2025 12:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6682991919,0cyclictest55650irq/125-lan12:01:421
6682991919,0cyclictest55650irq/125-lan11:35:161
6682991918,1cyclictest55650irq/125-lan11:54:321
6682991918,1cyclictest55650irq/125-lan11:07:271
6682991918,1cyclictest55650irq/125-lan10:15:181
6682991918,1cyclictest55650irq/125-lan09:35:121
6682991818,0cyclictest55650irq/125-lan12:31:051
6682991818,0cyclictest55650irq/125-lan12:15:421
6682991818,0cyclictest55650irq/125-lan12:12:581
6682991818,0cyclictest55650irq/125-lan11:57:221
6682991818,0cyclictest55650irq/125-lan11:48:311
6682991818,0cyclictest55650irq/125-lan11:20:081
6682991818,0cyclictest55650irq/125-lan11:11:031
6682991818,0cyclictest55650irq/125-lan11:03:001
6682991818,0cyclictest55650irq/125-lan10:59:191
6682991818,0cyclictest55650irq/125-lan10:45:481
6682991818,0cyclictest55650irq/125-lan10:33:201
6682991818,0cyclictest55650irq/125-lan10:26:041
6682991818,0cyclictest55650irq/125-lan10:07:591
6682991818,0cyclictest55650irq/125-lan10:03:511
6682991818,0cyclictest55650irq/125-lan09:59:481
6682991818,0cyclictest55650irq/125-lan09:45:231
6682991818,0cyclictest55650irq/125-lan09:23:471
6682991818,0cyclictest55650irq/125-lan09:12:471
6682991818,0cyclictest55650irq/125-lan08:15:421
6682991818,0cyclictest55650irq/125-lan07:59:331
6682991818,0cyclictest55650irq/125-lan07:54:441
6682991818,0cyclictest55650irq/125-lan07:36:291
6682991817,1cyclictest55650irq/125-lan12:29:181
6682991817,1cyclictest55650irq/125-lan11:25:471
6682991817,1cyclictest55650irq/125-lan11:18:201
6682991817,1cyclictest55650irq/125-lan10:36:281
6682991717,0cyclictest55650irq/125-lan12:36:421
6682991717,0cyclictest55650irq/125-lan12:21:571
6682991717,0cyclictest55650irq/125-lan12:08:511
6682991717,0cyclictest55650irq/125-lan11:44:311
6682991717,0cyclictest55650irq/125-lan11:31:521
6682991717,0cyclictest55650irq/125-lan10:40:131
6682991717,0cyclictest55650irq/125-lan10:21:311
6682991717,0cyclictest55650irq/125-lan10:12:341
6682991717,0cyclictest55650irq/125-lan09:41:411
6682991717,0cyclictest55650irq/125-lan09:30:071
6682991717,0cyclictest55650irq/125-lan09:27:151
6682991717,0cyclictest55650irq/125-lan08:50:291
6682991717,0cyclictest55650irq/125-lan07:30:181
6682991716,1cyclictest55650irq/125-lan09:51:031
6682991716,1cyclictest55650irq/125-lan09:16:291
6682991715,1cyclictest55650irq/125-lan10:50:141
6682991616,0cyclictest55650irq/125-lan09:01:081
6682991616,0cyclictest55650irq/125-lan08:55:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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