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2024-11-22 - 06:15

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot7s.osadl.org (updated Fri Nov 22, 2024 00:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16982992019,1cyclictest55650irq/125-lan21:15:011
16982992019,1cyclictest55650irq/125-lan20:07:281
16982992018,1cyclictest55650irq/125-lan22:15:151
16982992018,1cyclictest55650irq/125-lan21:30:431
16982991918,1cyclictest55650irq/125-lan23:50:551
16982991918,1cyclictest55650irq/125-lan23:49:491
16982991918,1cyclictest55650irq/125-lan23:37:151
16982991918,1cyclictest55650irq/125-lan23:06:301
16982991918,1cyclictest55650irq/125-lan23:03:141
16982991918,1cyclictest55650irq/125-lan22:33:191
16982991918,1cyclictest55650irq/125-lan22:10:411
16982991918,1cyclictest55650irq/125-lan21:51:261
16982991918,1cyclictest55650irq/125-lan21:43:401
16982991918,1cyclictest55650irq/125-lan21:26:081
16982991918,1cyclictest55650irq/125-lan19:56:551
16982991918,1cyclictest55650irq/125-lan19:39:581
16982991918,1cyclictest55650irq/125-lan00:38:041
16982991918,1cyclictest55650irq/125-lan00:34:241
16982991918,1cyclictest55650irq/125-lan00:25:191
16982991917,2cyclictest55650irq/125-lan22:20:131
16982991818,0cyclictest55650irq/125-lan23:25:461
16982991818,0cyclictest55650irq/125-lan21:37:431
16982991818,0cyclictest55650irq/125-lan00:07:261
16982991817,1cyclictest55650irq/125-lan23:56:351
16982991817,1cyclictest55650irq/125-lan23:40:251
16982991817,1cyclictest55650irq/125-lan23:31:021
16982991817,1cyclictest55650irq/125-lan23:21:521
16982991817,1cyclictest55650irq/125-lan23:15:091
16982991817,1cyclictest55650irq/125-lan23:13:091
16982991817,1cyclictest55650irq/125-lan22:55:061
16982991817,1cyclictest55650irq/125-lan22:52:381
16982991817,1cyclictest55650irq/125-lan22:44:531
16982991817,1cyclictest55650irq/125-lan22:37:001
16982991817,1cyclictest55650irq/125-lan22:27:261
16982991817,1cyclictest55650irq/125-lan22:06:101
16982991817,1cyclictest55650irq/125-lan21:48:161
16982991817,1cyclictest55650irq/125-lan21:22:421
16982991817,1cyclictest55650irq/125-lan21:10:541
16982991817,1cyclictest55650irq/125-lan20:55:191
16982991817,1cyclictest55650irq/125-lan20:40:221
16982991817,1cyclictest55650irq/125-lan20:25:001
16982991817,1cyclictest55650irq/125-lan20:12:541
16982991817,1cyclictest55650irq/125-lan19:30:501
16982991817,1cyclictest55650irq/125-lan19:23:341
16982991817,1cyclictest55650irq/125-lan19:18:141
16982991817,1cyclictest55650irq/125-lan00:22:161
16982991817,1cyclictest55650irq/125-lan00:10:541
16982991817,1cyclictest55650irq/125-lan00:03:371
16982991717,0cyclictest55650irq/125-lan00:15:051
16982991716,1cyclictest55650irq/125-lan22:45:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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