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2025-04-02 - 05:01

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7s.osadl.org (updated Wed Apr 02, 2025 00:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21562991918,1cyclictest55650irq/125-lan23:46:451
21562991918,1cyclictest55650irq/125-lan23:29:491
21562991918,1cyclictest55650irq/125-lan23:15:141
21562991918,1cyclictest55650irq/125-lan23:08:171
21562991918,1cyclictest55650irq/125-lan22:41:561
21562991918,1cyclictest55650irq/125-lan21:50:051
21562991918,1cyclictest55650irq/125-lan21:45:401
21562991918,1cyclictest55650irq/125-lan21:43:451
21562991918,1cyclictest55650irq/125-lan21:30:201
21562991918,1cyclictest55650irq/125-lan21:17:291
21562991918,1cyclictest55650irq/125-lan19:37:261
21562991918,1cyclictest55650irq/125-lan00:37:131
21562991917,1cyclictest55650irq/125-lan23:24:491
21562991917,1cyclictest55650irq/125-lan22:46:331
21562991818,0cyclictest55650irq/125-lan23:56:001
21562991818,0cyclictest55650irq/125-lan23:41:471
21562991818,0cyclictest55650irq/125-lan21:07:571
21562991818,0cyclictest55650irq/125-lan00:26:491
21562991817,1cyclictest55650irq/125-lan23:51:051
21562991817,1cyclictest55650irq/125-lan23:39:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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