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2024-11-24 - 07:49

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack8slot7s.osadl.org (updated Sun Nov 24, 2024 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19283992121,0cyclictest55650irq/125-lan23:17:001
19283992020,0cyclictest55650irq/125-lan23:36:071
19283992020,0cyclictest55650irq/125-lan22:16:031
19283992020,0cyclictest55650irq/125-lan21:40:551
19283992020,0cyclictest55650irq/125-lan00:22:011
19283992019,1cyclictest55650irq/125-lan23:09:281
19283992019,1cyclictest55650irq/125-lan22:27:311
19283991919,0cyclictest55650irq/125-lan23:48:581
19283991919,0cyclictest55650irq/125-lan23:26:321
19283991919,0cyclictest55650irq/125-lan23:12:101
19283991919,0cyclictest55650irq/125-lan21:34:481
19283991919,0cyclictest55650irq/125-lan00:29:041
19283991919,0cyclictest55650irq/125-lan00:02:231
19283991918,1cyclictest55650irq/125-lan23:21:231
19283991918,1cyclictest55650irq/125-lan23:05:011
19283991918,1cyclictest55650irq/125-lan22:14:281
19283991918,1cyclictest55650irq/125-lan20:31:201
19283991918,1cyclictest55650irq/125-lan00:34:591
19283991917,1cyclictest55650irq/125-lan00:10:211
19283991818,0cyclictest55650irq/125-lan23:55:051
19283991818,0cyclictest55650irq/125-lan23:44:541
19283991818,0cyclictest55650irq/125-lan23:32:301
19283991818,0cyclictest55650irq/125-lan22:50:231
19283991818,0cyclictest55650irq/125-lan22:40:071
19283991818,0cyclictest55650irq/125-lan22:34:261
19283991818,0cyclictest55650irq/125-lan21:56:221
19283991818,0cyclictest55650irq/125-lan21:24:201
19283991818,0cyclictest55650irq/125-lan21:13:431
19283991818,0cyclictest55650irq/125-lan21:05:161
19283991818,0cyclictest55650irq/125-lan20:43:511
19283991818,0cyclictest55650irq/125-lan00:35:101
19283991818,0cyclictest55650irq/125-lan00:08:531
19283991817,1cyclictest55650irq/125-lan23:54:151
19283991817,1cyclictest55650irq/125-lan22:55:131
19283991817,1cyclictest55650irq/125-lan22:46:251
19283991817,1cyclictest55650irq/125-lan22:35:151
19283991817,1cyclictest55650irq/125-lan22:21:481
19283991817,1cyclictest55650irq/125-lan21:51:081
19283991817,1cyclictest55650irq/125-lan21:46:341
19283991817,1cyclictest55650irq/125-lan21:25:441
19283991817,1cyclictest55650irq/125-lan20:45:161
19283991817,1cyclictest55650irq/125-lan20:10:191
19283991816,2cyclictest55650irq/125-lan00:15:041
19283991816,1cyclictest55650irq/125-lan21:35:131
19283991717,0cyclictest55650irq/125-lan22:06:511
19283991717,0cyclictest55650irq/125-lan22:01:021
19283991717,0cyclictest55650irq/125-lan21:15:021
19283991717,0cyclictest55650irq/125-lan20:37:461
19283991717,0cyclictest55650irq/125-lan20:25:211
19283991717,0cyclictest55650irq/125-lan20:23:211
19283991717,0cyclictest55650irq/125-lan20:18:191
19283991717,0cyclictest55650irq/125-lan20:03:041
19283991717,0cyclictest55650irq/125-lan19:44:131
19283991717,0cyclictest55650irq/125-lan19:35:161
19283991717,0cyclictest55650irq/125-lan19:27:261
19283991717,0cyclictest55650irq/125-lan19:20:171
19283991616,0cyclictest55650irq/125-lan20:59:181
19283991616,0cyclictest55650irq/125-lan20:06:371
19283991616,0cyclictest55650irq/125-lan19:58:011
19283991616,0cyclictest55650irq/125-lan19:30:271
19283991615,1cyclictest55650irq/125-lan19:15:281
19283991615,1cyclictest55650irq/125-lan19:11:371
19283991515,0cyclictest55650irq/125-lan21:01:491
19283991515,0cyclictest55650irq/125-lan20:50:391
19279991515,0cyclictest294-21hwrng22:45:310
19283991414,0cyclictest55650irq/125-lan19:52:591
19283991413,1cyclictest55650irq/125-lan19:45:331
1927999109,1cyclictest29438-21proc_pri22:50:230
192799998,1cyclictest703-21snmpd23:44:530
192799998,1cyclictest703-21snmpd19:47:270
192799998,1cyclictest703-21snmpd00:02:380
192799998,1cyclictest25678-21ntp_kernel_err23:20:170
192799998,1cyclictest14023-21/usr/sbin/munin20:25:010
192799996,2cyclictest703-21snmpd22:03:370
192799996,2cyclictest703-21snmpd19:18:170
192799988,0cyclictest703-21snmpd21:52:460
192799988,0cyclictest703-21snmpd20:53:560
192799988,0cyclictest703-21snmpd20:18:460
192799988,0cyclictest294-21hwrng23:54:090
192799988,0cyclictest294-21hwrng23:26:290
192799988,0cyclictest294-21hwrng23:13:100
192799988,0cyclictest294-21hwrng23:06:010
192799988,0cyclictest294-21hwrng22:55:470
192799988,0cyclictest294-21hwrng22:05:350
192799988,0cyclictest294-21hwrng21:07:140
192799988,0cyclictest294-21hwrng20:31:230
192799988,0cyclictest294-21hwrng20:25:150
192799988,0cyclictest294-21hwrng20:11:560
192799988,0cyclictest294-21hwrng19:58:370
192799988,0cyclictest294-21hwrng19:31:590
192799988,0cyclictest294-21hwrng19:20:440
192799988,0cyclictest294-21hwrng00:20:460
192799987,1cyclictest703-21snmpd22:22:240
192799987,1cyclictest703-21snmpd20:06:450
192799987,1cyclictest703-21snmpd00:17:430
192799987,1cyclictest5806-21ntp_kernel_pll_22:25:170
192799987,1cyclictest478-21gmain19:35:110
192799986,2cyclictest703-21snmpd23:04:010
192799986,2cyclictest703-21snmpd22:37:470
192799986,2cyclictest703-21snmpd21:22:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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