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2024-11-22 - 17:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot7.osadl.org (updated Fri Nov 22, 2024 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15445992727,0cyclictest29131-21fwupd07:43:162
15436992019,1cyclictest60250irq/125-lan09:36:080
15436991919,0cyclictest60250irq/125-lan10:54:260
15436991919,0cyclictest60250irq/125-lan09:57:480
15436991918,1cyclictest60250irq/125-lan11:10:210
15436991918,1cyclictest60250irq/125-lan10:40:000
15436991918,1cyclictest60250irq/125-lan10:20:130
15436991918,1cyclictest60250irq/125-lan10:15:120
15436991918,1cyclictest60250irq/125-lan10:05:390
15436991918,1cyclictest60250irq/125-lan09:40:170
15436991918,1cyclictest60250irq/125-lan09:18:080
15436991918,1cyclictest60250irq/125-lan08:15:130
15436991818,0cyclictest60250irq/125-lan12:25:510
15436991818,0cyclictest60250irq/125-lan12:15:190
15436991818,0cyclictest60250irq/125-lan11:56:260
15436991818,0cyclictest60250irq/125-lan11:46:040
15436991818,0cyclictest60250irq/125-lan11:20:340
15436991818,0cyclictest60250irq/125-lan11:01:470
15436991817,1cyclictest60250irq/125-lan12:39:300
15436991817,1cyclictest60250irq/125-lan12:14:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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