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2024-11-22 - 05:42

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot6s.osadl.org (updated Fri Nov 22, 2024 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26019992219,1cyclictest61550irq/125-lan23:35:192
26019992118,1cyclictest61550irq/125-lan22:21:082
26019992118,1cyclictest61550irq/125-lan21:40:172
26019992118,0cyclictest61550irq/125-lan22:54:332
26019992018,0cyclictest61550irq/125-lan23:55:122
26019992018,0cyclictest61550irq/125-lan23:09:502
26019992018,0cyclictest61550irq/125-lan22:32:422
26016992020,0cyclictest331-21hwrng23:04:321
26019991918,1cyclictest61550irq/125-lan23:29:522
26019991918,1cyclictest61550irq/125-lan23:17:482
26019991918,1cyclictest61550irq/125-lan23:02:312
26019991918,1cyclictest61550irq/125-lan22:07:012
26019991918,1cyclictest61550irq/125-lan21:55:162
26019991918,1cyclictest61550irq/125-lan21:47:442
26019991818,0cyclictest61550irq/125-lan22:03:152
26019991818,0cyclictest61550irq/125-lan21:20:142
26019991817,1cyclictest61550irq/125-lan23:51:202
26019991817,1cyclictest61550irq/125-lan23:42:102
26019991817,1cyclictest61550irq/125-lan23:30:182
26019991817,1cyclictest61550irq/125-lan22:10:152
26019991817,1cyclictest61550irq/125-lan21:25:362
26019991817,1cyclictest61550irq/125-lan19:55:202
26019991817,1cyclictest61550irq/125-lan00:08:362
26019991816,1cyclictest61550irq/125-lan23:23:212
26019991816,1cyclictest61550irq/125-lan22:16:202
26019991816,1cyclictest61550irq/125-lan21:16:382
26019991816,1cyclictest61550irq/125-lan00:15:202
26016991818,0cyclictest716-21snmpd19:25:081
26019991717,0cyclictest61550irq/125-lan23:47:402
26019991717,0cyclictest61550irq/125-lan22:43:192
26019991717,0cyclictest61550irq/125-lan22:25:012
26019991717,0cyclictest61550irq/125-lan20:45:142
26019991717,0cyclictest61550irq/125-lan00:36:232
26019991717,0cyclictest61550irq/125-lan00:00:112
26019991716,1cyclictest61550irq/125-lan22:55:142
26019991716,1cyclictest61550irq/125-lan21:50:222
26019991716,1cyclictest61550irq/125-lan21:35:112
26019991716,1cyclictest61550irq/125-lan21:30:032
26019991716,1cyclictest61550irq/125-lan20:50:152
26019991716,1cyclictest61550irq/125-lan20:25:192
26019991716,1cyclictest61550irq/125-lan19:10:142
26019991716,1cyclictest61550irq/125-lan00:32:292
26019991716,1cyclictest61550irq/125-lan00:22:212
26019991716,1cyclictest61550irq/125-lan00:10:192
26016991717,0cyclictest716-21snmpd23:47:361
26019991616,0cyclictest61550irq/125-lan22:35:492
26019991616,0cyclictest61550irq/125-lan20:55:132
26019991616,0cyclictest61550irq/125-lan19:25:152
26019991616,0cyclictest61550irq/125-lan00:29:282
26019991615,1cyclictest61550irq/125-lan23:10:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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