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2025-04-03 - 15:40

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack8slot6s.osadl.org (updated Thu Apr 03, 2025 12:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30468993131,0cyclictest29775-21fwupd08:44:133
30468991818,0cyclictest765-21snmpd12:32:323
30468991818,0cyclictest765-21snmpd12:32:323
30468991818,0cyclictest765-21snmpd10:13:363
30468991818,0cyclictest765-21snmpd08:05:593
30468991818,0cyclictest739-21ntpd11:10:133
30468991818,0cyclictest65850irq/126-lan12:13:573
30468991818,0cyclictest65850irq/126-lan11:58:193
30468991818,0cyclictest65850irq/126-lan11:30:003
30468991818,0cyclictest65850irq/126-lan10:59:573
30468991818,0cyclictest65850irq/126-lan10:50:163
30468991818,0cyclictest65850irq/126-lan09:46:213
30468991818,0cyclictest65850irq/126-lan09:36:323
30468991818,0cyclictest2964-21cat10:35:123
30468991817,1cyclictest65850irq/126-lan12:09:193
30468991817,1cyclictest65850irq/126-lan11:52:183
30468991817,1cyclictest65850irq/126-lan11:31:143
30468991817,1cyclictest65850irq/126-lan11:15:143
30468991817,1cyclictest65850irq/126-lan10:48:483
30468991817,1cyclictest65850irq/126-lan10:05:133
30468991817,1cyclictest65850irq/126-lan09:53:163
30468991817,1cyclictest65850irq/126-lan09:20:153
30468991717,0cyclictest765-21snmpd09:55:473
30468991717,0cyclictest765-21snmpd07:36:503
30468991717,0cyclictest739-21ntpd12:28:263
30468991717,0cyclictest739-21ntpd12:15:123
30468991717,0cyclictest739-21ntpd11:40:163
30468991717,0cyclictest739-21ntpd11:37:493
30468991717,0cyclictest739-21ntpd11:00:513
30468991717,0cyclictest739-21ntpd10:30:183
30468991717,0cyclictest739-21ntpd07:20:193
30468991717,0cyclictest65850irq/126-lan11:23:223
30468991717,0cyclictest65850irq/126-lan10:42:323
30468991717,0cyclictest65850irq/126-lan10:17:233
30468991717,0cyclictest65850irq/126-lan09:40:573
30468991717,0cyclictest65850irq/126-lan09:34:083
30468991717,0cyclictest65850irq/126-lan09:14:243
30468991717,0cyclictest65850irq/126-lan09:03:113
30468991717,0cyclictest65850irq/126-lan08:48:343
30468991717,0cyclictest65850irq/126-lan08:37:443
30468991717,0cyclictest65850irq/126-lan08:16:233
30468991716,1cyclictest65850irq/126-lan12:36:163
30468991716,1cyclictest65850irq/126-lan12:20:013
30468991716,1cyclictest65850irq/126-lan11:06:263
30468991716,1cyclictest65850irq/126-lan10:25:093
30468991716,1cyclictest65850irq/126-lan10:02:203
30468991716,1cyclictest65850irq/126-lan09:16:283
30468991716,1cyclictest65850irq/126-lan07:30:243
30468991616,0cyclictest65850irq/126-lan11:47:073
30468991616,0cyclictest65850irq/126-lan10:20:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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