You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-07-16 - 15:53

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot6s.osadl.org (updated Tue Jul 16, 2024 12:43:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15666992424,0cyclictest16243-21fwupd11:56:071
15662992323,0cyclictest331-21hwrng09:18:580
15670991918,1cyclictest61550irq/125-lan11:17:312
15670991918,1cyclictest61550irq/125-lan11:05:182
15670991918,1cyclictest61550irq/125-lan09:53:492
15670991917,1cyclictest61550irq/125-lan09:35:222
15670991818,0cyclictest61550irq/125-lan12:28:242
15670991818,0cyclictest61550irq/125-lan12:05:222
15670991818,0cyclictest61550irq/125-lan11:30:142
15670991818,0cyclictest61550irq/125-lan11:26:472
15670991818,0cyclictest61550irq/125-lan11:24:142
15670991818,0cyclictest61550irq/125-lan11:04:002
15670991818,0cyclictest61550irq/125-lan10:55:302
15670991818,0cyclictest61550irq/125-lan10:30:142
15670991818,0cyclictest61550irq/125-lan10:18:242
15670991818,0cyclictest61550irq/125-lan10:02:442
15670991818,0cyclictest61550irq/125-lan09:41:142
15670991818,0cyclictest61550irq/125-lan09:29:572
15670991817,1cyclictest61550irq/125-lan12:22:402
15670991817,1cyclictest61550irq/125-lan12:15:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional