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2024-11-23 - 17:26

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #8, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot6s.osadl.org (updated Sat Nov 23, 2024 12:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11130991919,0cyclictest61550irq/125-lan11:02:572
11130991918,1cyclictest61550irq/125-lan12:15:222
11130991918,1cyclictest61550irq/125-lan11:50:182
11130991918,1cyclictest61550irq/125-lan11:35:372
11130991918,1cyclictest61550irq/125-lan11:30:142
11130991918,1cyclictest61550irq/125-lan09:49:212
11130991918,1cyclictest61550irq/125-lan07:55:152
11130991818,0cyclictest61550irq/125-lan12:12:252
11130991818,0cyclictest61550irq/125-lan12:00:082
11130991818,0cyclictest61550irq/125-lan10:41:162
11130991818,0cyclictest61550irq/125-lan10:20:142
11130991818,0cyclictest61550irq/125-lan10:03:562
11130991818,0cyclictest61550irq/125-lan09:45:002
11130991818,0cyclictest61550irq/125-lan09:34:012
11130991818,0cyclictest61550irq/125-lan09:16:042
11130991818,0cyclictest61550irq/125-lan07:31:362
11130991817,1cyclictest61550irq/125-lan12:37:512
11130991817,1cyclictest61550irq/125-lan12:25:172
11130991817,1cyclictest61550irq/125-lan11:56:312
11130991817,1cyclictest61550irq/125-lan11:40:512
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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