You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-11-21 - 16:40
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack8slot5.osadl.org (updated Thu Nov 21, 2024 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,6586
"cycles":100000000,6585
"load":"idle",6584
"condition":{6583
"clock":"3400"6581
"family":"x86",6580
"vendor":"Intel",6579
"processor":{6577
"dataset":"2024-01-08T15:37:47+0100"6575
"origin":"2024-01-08T12:43:21+0100",6574
"timestamps":{6573
"granularity":"microseconds"6571
2013:51:116569
18,13:51:096568
18,13:51:096567
19,13:51:106566
18,13:51:096565
18,13:51:096564
18,13:51:096563
18,13:51:096562
"maxima":[6561
013:50:516558
0,13:50:516557
0,13:50:516556
0,13:50:516555
0,13:50:516554
0,13:50:516553
0,13:50:516552
0,13:50:516551
0,13:50:516550
0,13:50:516549
0,13:50:516548
0,13:50:516547
0,13:50:516546
0,13:50:516545
0,13:50:516544
0,13:50:516543
0,13:50:516542
0,13:50:516541
0,13:50:516540
0,13:50:516539
0,13:50:516538
0,13:50:516537
0,13:50:516536
0,13:50:516535
0,13:50:516534
0,13:50:516533
0,13:50:516532
0,13:50:516531
0,13:50:516530
0,13:50:516529
0,13:50:516528
0,13:50:516527
0,13:50:516526
0,13:50:516525
0,13:50:516524
0,13:50:516523
0,13:50:516522
0,13:50:516521
0,13:50:516520
0,13:50:516519
0,13:50:516518
0,13:50:516517
0,13:50:516516
0,13:50:516515
0,13:50:516514
0,13:50:516513
0,13:50:516512
0,13:50:516511
0,13:50:516510
0,13:50:516509
0,13:50:516508
0,13:50:516507
0,13:50:516506
0,13:50:516505
0,13:50:516504
0,13:50:516503
0,13:50:516502
0,13:50:516501
0,13:50:516500
0,13:50:516499
0,13:50:516498
0,13:50:516497
0,13:50:516496
0,13:50:516495
0,13:50:516494
0,13:50:516493
0,13:50:516492
0,13:50:516491
0,13:50:516490
0,13:50:516489
0,13:50:516488
0,13:50:516487
0,13:50:516486
0,13:50:516485
0,13:50:516484
0,13:50:516483
0,13:50:516482
0,13:50:516481
0,13:50:516480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional