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2024-07-16 - 08:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot1.osadl.org (updated Mon Jul 15, 2024 12:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8615211858,20sleep30-21swapper/307:07:363
8572211554,56sleep20-21swapper/207:07:042
8586211451,58sleep10-21swapper/107:07:141
8804211050,20sleep00-21swapper/007:09:590
8903995332,18cyclictest0-21swapper/312:38:533
8903995231,18cyclictest0-21swapper/312:26:213
8903995131,17cyclictest0-21swapper/312:12:253
8903995034,14cyclictest0-21swapper/311:41:323
8903995034,14cyclictest0-21swapper/311:41:323
8903995031,16cyclictest0-21swapper/309:53:483
8903995031,16cyclictest0-21swapper/309:53:473
8903994934,12cyclictest0-21swapper/309:31:153
8903994932,15cyclictest0-21swapper/311:14:083
8903994932,14cyclictest0-21swapper/309:10:483
8903994932,14cyclictest0-21swapper/309:10:483
8903994931,16cyclictest0-21swapper/311:53:263
8903994833,13cyclictest0-21swapper/312:20:293
8903994833,12cyclictest0-21swapper/311:05:413
8903994833,12cyclictest0-21swapper/311:05:403
8903994832,14cyclictest0-21swapper/310:03:563
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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