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2024-11-22 - 10:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot1.osadl.org (updated Fri Nov 22, 2024 00:45:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27471211855,58sleep10-21swapper/119:06:001
27688211452,24sleep30-21swapper/319:08:423
27597211352,55sleep20-21swapper/219:07:332
2745929250,37sleep00-21swapper/019:05:500
169942580,1sleep015465-21stress22:26:320
27890994730,15cyclictest0-21swapper/023:56:070
27890994529,13cyclictest0-21swapper/021:36:090
27890994527,15cyclictest0-21swapper/023:10:220
27890994526,16cyclictest0-21swapper/023:27:460
27890994428,14cyclictest0-21swapper/022:20:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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