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2024-07-16 - 08:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack7slot0.osadl.org (updated Mon Jul 15, 2024 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050640,0irq/25-eth00-21swapper/107:08:531
117950620,0irq/26-eth1-rx-0-21swapper/307:08:533
110050560,0irq/25-eth00-21swapper/207:05:562
110050450,0irq/25-eth00-21swapper/007:05:370
110050210,0irq/25-eth07099-21id12:14:203
41180,0ktimersoftd/00-21swapper/010:37:100
351180,0ktimersoftd/322670-21sshd10:37:113
1365299170,0cyclictest0-21swapper/311:46:413
1365199160,0cyclictest0-21swapper/208:30:182
13650991614,0cyclictest9295-21sshd11:01:301
13652991512,0cyclictest0-21swapper/309:22:523
1365299150,0cyclictest0-21swapper/310:23:173
1365299150,0cyclictest0-21swapper/307:15:013
13650991514,0cyclictest0-21swapper/111:48:591
13650991512,0cyclictest0-21swapper/110:28:291
1365099150,0cyclictest0-21swapper/111:16:341
13649991514,0cyclictest0-21swapper/010:57:150
1364999150,0cyclictest0-21swapper/009:16:530
13652991413,0cyclictest0-21swapper/310:10:153
13650991413,0cyclictest0-21swapper/112:32:331
13649991411,0cyclictest7673-21sshd09:28:160
1364999140,0cyclictest0-21swapper/009:43:430
191130,0ktimersoftd/13652-21sshd09:18:401
13652991312,0cyclictest25805-21sshd09:12:383
13652991311,0cyclictest0-21swapper/309:42:223
13651991312,0cyclictest4880-21users11:30:372
13651991312,0cyclictest0-21swapper/212:38:362
13651991312,0cyclictest0-21swapper/210:46:292
13651991312,0cyclictest0-21swapper/210:40:262
13651991312,0cyclictest0-21swapper/210:16:102
13651991312,0cyclictest0-21swapper/209:35:302
13651991311,0cyclictest0-21swapper/211:49:402
1365199130,0cyclictest19755-21bash12:07:202
13650991312,0cyclictest0-21swapper/111:33:041
13650991311,0cyclictest29919-21sshd11:25:281
1365099130,0cyclictest0-21swapper/112:14:321
13649991312,0cyclictest5624-21diskmemload10:33:540
1364999130,0cyclictest0-21swapper/010:20:460
1364999130,0cyclictest0-21swapper/007:20:360
13652991212,0cyclictest0-21swapper/310:48:563
13652991212,0cyclictest0-21swapper/310:27:143
13652991211,0cyclictest0-21swapper/311:57:283
13652991211,0cyclictest0-21swapper/311:35:533
13652991211,0cyclictest0-21swapper/311:25:043
13652991211,0cyclictest0-21swapper/311:05:543
13652991211,0cyclictest0-21swapper/310:54:243
13652991210,0cyclictest0-21swapper/311:11:573
1365299120,0cyclictest0-21swapper/312:19:323
1365299120,0cyclictest0-21swapper/311:22:303
1365299120,0cyclictest0-21swapper/310:34:323
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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