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2025-04-02 - 04:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Wed Apr 02, 2025 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050660,0irq/25-eth00-21swapper/319:05:203
117950590,0irq/26-eth1-rx-0-21swapper/119:07:491
110050560,0irq/25-eth00-21swapper/219:08:052
117950460,0irq/26-eth1-rx-0-21swapper/019:05:190
9950170,0irq/24-0000:00:3-21ksoftirqd/000:18:240
30156991614,0cyclictest7544-21munin-run00:00:002
30157991512,0cyclictest0-21swapper/322:11:453
3015499153,0cyclictest0-21swapper/022:20:160
30157991411,0cyclictest0-21swapper/300:18:433
3015799140,0cyclictest0-21swapper/300:31:373
30156991413,0cyclictest0-21swapper/222:04:432
3015699140,0cyclictest0-21swapper/221:26:372
3015699140,0cyclictest0-21swapper/221:05:142
3015699140,0cyclictest0-21swapper/219:20:162
30155991413,0cyclictest9643-21sshd23:56:471
30155991411,0cyclictest4786-21sshd21:18:331
3015599140,0cyclictest4579-21sshd22:08:441
3015599140,0cyclictest0-21swapper/121:12:531
30154991413,0cyclictest0-21swapper/021:17:280
3015499141,0cyclictest0-21swapper/023:30:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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