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2024-11-22 - 17:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack7slot0.osadl.org (updated Fri Nov 22, 2024 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050590,0irq/25-eth00-21swapper/107:05:591
117950560,0irq/26-eth1-rx-0-21swapper/307:05:463
110050550,0irq/25-eth00-21swapper/207:06:492
2019924621,0sleep00-21swapper/007:05:520
110050170,0irq/25-eth00-21swapper/310:41:183
2060499160,0cyclictest0-21swapper/210:51:152
20603991614,0cyclictest0-21swapper/110:29:531
20605991514,0cyclictest0-21swapper/312:20:163
2060499150,0cyclictest0-21swapper/212:21:442
2060399150,0cyclictest12592-21diskmemload10:57:191
110050150,0irq/25-eth03450-21sshd10:28:173
351140,0ktimersoftd/312415-21bash11:50:183
351140,0ktimersoftd/312415-21bash11:50:173
20605991411,0cyclictest12592-21diskmemload11:45:593
2060599140,0cyclictest110050irq/25-eth010:36:243
2060599140,0cyclictest0-21swapper/309:39:583
20604991413,0cyclictest29274-21sshd11:39:052
20604991413,0cyclictest0-21swapper/210:55:592
2060299144,0cyclictest0-21swapper/010:20:150
20602991412,0cyclictest0-21swapper/010:18:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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