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2024-07-16 - 08:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Mon Jul 15, 2024 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
110050640,0irq/25-eth00-21swapper/107:08:531
117950620,0irq/26-eth1-rx-0-21swapper/307:08:533
110050560,0irq/25-eth00-21swapper/207:05:562
110050450,0irq/25-eth00-21swapper/007:05:370
110050210,0irq/25-eth07099-21id12:14:203
41180,0ktimersoftd/00-21swapper/010:37:100
351180,0ktimersoftd/322670-21sshd10:37:113
1365299170,0cyclictest0-21swapper/311:46:413
1365199160,0cyclictest0-21swapper/208:30:182
13650991614,0cyclictest9295-21sshd11:01:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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