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2024-11-25 - 14:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack7slot0.osadl.org (updated Mon Nov 25, 2024 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117950590,0irq/26-eth1-rx-0-21swapper/307:06:263
117950590,0irq/26-eth1-rx-0-21swapper/107:08:211
110050560,0irq/25-eth00-21swapper/207:08:202
117950450,0irq/26-eth1-rx-0-21swapper/007:09:500
17148993110,0cyclictest13460-21bash11:38:051
1715099170,0cyclictest677-21sshd12:19:263
110050170,0irq/25-eth036-21ksoftirqd/311:55:093
1715099150,0cyclictest9078-21diskmemload12:14:403
17147991512,0cyclictest0-21swapper/010:05:140
1714799150,0cyclictest31576-21bash09:34:410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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