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2025-04-02 - 04:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Apr 02, 2025 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1509199708699,7cyclictest4927-21kerneloops23:37:160
1509799707700,5cyclictest4927-21kerneloops20:32:441
1509799707699,6cyclictest4927-21kerneloops20:55:301
1509799707698,7cyclictest4927-21kerneloops20:39:261
1509199707697,8cyclictest4927-21kerneloops23:19:290
1510199706697,7cyclictest4927-21kerneloops19:44:082
1509799706702,2cyclictest4927-21kerneloops19:24:581
1509199706696,8cyclictest4927-21kerneloops21:17:290
1510999705702,2cyclictest4927-21kerneloops21:38:343
1510999705700,4cyclictest4927-21kerneloops19:59:313
1510199705697,6cyclictest4927-21kerneloops22:07:062
1509799705701,2cyclictest4927-21kerneloops21:48:381
1509199705698,6cyclictest4927-21kerneloops21:45:560
1510199704698,5cyclictest4927-21kerneloops00:29:562
1510199704697,5cyclictest4927-21kerneloops22:00:092
1510199704696,6cyclictest4927-21kerneloops19:46:342
1510199704696,6cyclictest4927-21kerneloops00:00:422
1510199704696,6cyclictest4927-21kerneloops00:00:422
1509799704701,2cyclictest4927-21kerneloops21:10:471
1509199704696,7cyclictest4927-21kerneloops22:48:390
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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