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2024-11-22 - 16:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri Nov 22, 2024 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2311599709701,6cyclictest4927-21kerneloops12:19:493
2311599708701,5cyclictest4927-21kerneloops07:50:413
2310099708701,5cyclictest4927-21kerneloops11:05:321
2309399708699,7cyclictest4927-21kerneloops10:08:200
2310099707696,9cyclictest4927-21kerneloops09:05:131
2309399707698,7cyclictest4927-21kerneloops08:15:040
2309399707695,10cyclictest4927-21kerneloops09:35:030
2311599706699,5cyclictest4927-21kerneloops09:18:373
2310099706699,5cyclictest4927-21kerneloops11:41:041
2309399706697,7cyclictest4927-21kerneloops12:20:420
2311599705701,2cyclictest4927-21kerneloops08:43:253
2311599705701,2cyclictest4927-21kerneloops08:43:243
2310899705698,5cyclictest4927-21kerneloops09:34:542
2310899705697,6cyclictest4927-21kerneloops11:11:122
2309399705694,10cyclictest4927-21kerneloops11:54:000
2310899704698,5cyclictest4927-21kerneloops08:17:152
2309399704698,5cyclictest4927-21kerneloops10:51:030
2311599703700,2cyclictest4927-21kerneloops11:04:483
2311599703700,1cyclictest4927-21kerneloops10:06:433
2310099703701,1cyclictest4927-21kerneloops11:10:401
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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