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2024-08-14 - 20:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Aug 14, 2024 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
973399663655,6cyclictest4927-21kerneloops07:50:173
972099660653,6cyclictest4927-21kerneloops09:19:151
973399659651,6cyclictest4927-21kerneloops12:15:213
972099659652,5cyclictest4927-21kerneloops11:17:411
971699659649,8cyclictest4927-21kerneloops12:22:010
973399658650,7cyclictest4927-21kerneloops08:51:253
972899658650,6cyclictest4927-21kerneloops10:40:442
971699658652,5cyclictest4927-21kerneloops09:26:000
973399657654,2cyclictest4927-21kerneloops08:25:443
973399657652,4cyclictest4927-21kerneloops09:16:293
973399657651,5cyclictest4927-21kerneloops11:52:063
973399657651,4cyclictest4927-21kerneloops10:15:103
973399657650,6cyclictest4927-21kerneloops08:38:523
972899656648,6cyclictest4927-21kerneloops10:20:202
971699656649,5cyclictest4927-21kerneloops08:15:460
973399655648,5cyclictest4927-21kerneloops09:53:333
972899655648,5cyclictest4927-21kerneloops08:05:032
972099655650,3cyclictest4927-21kerneloops07:28:081
972099655649,5cyclictest4927-21kerneloops08:29:051
971699655650,4cyclictest4927-21kerneloops09:12:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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